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    Magnetic random access memory
    2.
    发明授权
    Magnetic random access memory 失效
    磁性随机存取存储器

    公开(公告)号：US06842362B2

    公开(公告)日：2005-01-11

    申请号：US10368609

    申请日：2003-02-20

    申请人： Katsuyuki Fujita ,  Yoshihisa Iwata

    发明人： Katsuyuki Fujita ,  Yoshihisa Iwata

    IPC分类号： G11C11/15 ,  G11C8/08 ,  G11C11/16 ,  G11C11/00

    CPC分类号： G11C8/08 ,  G11C11/16

    摘要： One end of a write word line is connected to a decoder/driver unit. The decoder/driver unit is constituted by a P channel MOS transistor, an N channel MOS transistor, a differential amplifier, and an NAND circuit. When WRITE, CHRDY and RA1 all become “H”, an output signal from the NAND circuit becomes “H”, and a write current flows through the write word line. At this moment, a value of the write current is restricted to a value which does not exceed VLIMIT/R1 by the differential amplifier. R1 is a wiring resistance of the write word line.

    摘要翻译： 写字线的一端连接到解码器/驱动器单元。 解码器/驱动器单元由P沟道MOS晶体管，N沟道MOS晶体管，差分放大器和NAND电路构成。 当写入，CHRDY和RA1都变为“H”时，来自NAND电路的输出信号变为“H”，并且写入电流流过写入字线。 此时，写入电流的值被差分放大器限制为不超过VLIMIT / R1的值。 R1是写字线的布线电阻。

    Magnetic memory device and write/read method of the same
    3.
    发明授权
    Magnetic memory device and write/read method of the same 有权
    磁存储器件和写/读方法相同

    公开(公告)号：US07859881B2

    公开(公告)日：2010-12-28

    申请号：US11672261

    申请日：2007-02-07

    申请人： Yoshihisa Iwata ,  Katsuyuki Fujita ,  Yuui Shimizu

    发明人： Yoshihisa Iwata ,  Katsuyuki Fujita ,  Yuui Shimizu

    IPC分类号： G11C19/00

    CPC分类号： G11C19/0841 ,  G11C5/02 ,  G11C11/14 ,  G11C21/00 ,  Y10S977/933

    摘要： A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.

    摘要翻译： 一种磁存储器件包括：第一磁线，其具有由畴壁分隔的磁畴构成的多个单元，并且其中信息被记录在每个单元中，形成在第一磁线的一个端部处的第一写入元件，以及 形成在第一磁性线的另一端部的第一读取元件。

    Magnetic random access memory
    4.
    发明授权
    Magnetic random access memory 失效

    公开(公告)号：US06819585B2

    公开(公告)日：2004-11-16

    申请号：US10368456

    申请日：2003-02-20

    申请人： Katsuyuki Fujita ,  Yoshihisa Iwata

    发明人： Katsuyuki Fujita ,  Yoshihisa Iwata

    IPC分类号： G11C1100

    CPC分类号： G11C11/16 ,  G11C8/08

    摘要： One end of a write word line is connected to a decoder/driver unit. The decoder/driver unit is constituted by a P channel MOS transistor, an N channel MOS transistor, and an NAND circuit. When WRITE, CHRDY and RA1 all become “H”, an output signal from the NAND circuit becomes “H”, and a write current flows through the write word line. CHRDY is a signal which becomes “H” upon completion of an initialization operation of all internal circuits after turning on a power supply. A limiting circuit is constituted by a clamp circuit which limits a potential of a write word line to a fixed value or a lower value.

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08947918B2

    公开(公告)日：2015-02-03

    申请号：US14014231

    申请日：2013-08-29

    申请人： Katsuyuki Fujita

    发明人： Katsuyuki Fujita

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1673 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/1693

    摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command.

    摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，被配置为保持输入到输入/输出电路的数据并保持从存储单元阵列读取的数据的缓冲器以及被配置为接收第一命令和 来自外部的地址，并且响应于第一命令从耦合到由该地址指定的所选字线的存储器单元组读取数据到缓冲器。 控制器接收在第一命令之后输入的第二命令，并且指示包括写入命令和/或读取命令的一组命令的最后命令，并响应于第二命令从缓冲器开始到存储器单元阵列的写入操作 命令。

    Semiconductor memory device and driving method for the device
    8.
    发明授权
    Semiconductor memory device and driving method for the device 失效
    半导体存储器件及其驱动方法

    公开(公告)号：US07675793B2

    公开(公告)日：2010-03-09

    申请号：US12033258

    申请日：2008-02-19

    申请人： Katsuyuki Fujita

    发明人： Katsuyuki Fujita

    IPC分类号： G11C7/00

    CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C2211/4016

    摘要： This disclosure concerns a semiconductor memory device comprising: memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a bit line pair connected to the memory cells and transmitting data stored in the memory cells; a sense node pair connected to the bit line pair and transmitting data stored in the memory cells; transfer gates connected between the bit line pair and the sense node pair; latch circuits latching a high-level potential in one sense node of the sense node pair, and latching a first low-level potential in the other sense node of the sense node pair; and a level shifter applying a second low-level potential lower than the first low-level potential to one bit line of the bit line pair according to the electric potentials latched in the sense node pair at the time of writing data or writing back data.

    摘要翻译： 本公开涉及一种半导体存储器件，包括：存储单元，其包括存储数据的浮动体; 连接到存储器单元的门的字线; 连接到存储器单元并发送存储在存储单元中的数据的位线对; 感测节点对，连接到所述位线对并发送存储在所述存储单元中的数据; 连接在位线对和感测节点对之间的传输门; 锁存电路锁存感测节点对的一个感测节点中的高电平电位，并且锁存感测节点对的另一个感测节点中的第一低电平电位; 以及电平移位器，根据在写入数据或写入数据时锁存在感测节点对中的电位，将比第一低电平电位低的第二低电平电位施加到位线对的一个位线。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07539069B2

    公开(公告)日：2009-05-26

    申请号：US11748187

    申请日：2007-05-14

    申请人： Katsuyuki Fujita

    发明人： Katsuyuki Fujita

    IPC分类号： G11C7/00

    CPC分类号： G11C8/10 ,  G11C7/065 ,  G11C7/12 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2211/4016

    摘要： This disclosure concerns a memory comprising a memory cell; a first and a second sense nodes transmitting the data on the first and the second bit lines which transmits data with reversed polarities from each other; a first transfer gate provided between the first bit line and the first sense node; a second transfer gate provided between the second bit line and the second sense node; a latch circuit provided between the first and the second sense nodes; a write signal line activated when the data is written or restore to the cell; and a gate circuit connecting the write signal line to the first bit line and the first sense node to the second bit line, or connecting the write signal line to the second bit line and the second sense node to the first bit line, when the data is written or restore.

    摘要翻译： 本公开涉及包括存储器单元的存储器; 第一和第二感测节点，以相反极性传输数据的第一和第二位线发送数据; 设置在第一位线和第一感测节点之间的第一传送门; 提供在第二位线和第二感测节点之间的第二传输门; 设置在第一和第二感测节点之间的锁存电路; 当数据被写入或恢复到单元时，写入信号线被激活; 以及门电路，其将所述写信号线与所述第一位线和所述第一感测节点连接到所述第二位线，或者当所述数据与所述第一位线连接时，将所述写入信号线连接到所述第二位线和所述第二感测节点到所述第一位线 是写或还原。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07269084B2

    公开(公告)日：2007-09-11

    申请号：US11056243

    申请日：2005-02-14

    申请人： Kosuke Hatsuda ,  Takashi Ohsawa ,  Katsuyuki Fujita

    发明人： Kosuke Hatsuda ,  Takashi Ohsawa ,  Katsuyuki Fujita

    IPC分类号： G11C7/02

    CPC分类号： G11C7/14 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2211/4016

    摘要： The disclosure concerns a semiconductor memory device that includes memory cells that store data by accumulating or discharging an electric charge; memory cell arrays having a plurality of the memory cells disposed in a matrix; a plurality of word lines connected to the memory cells arrayed in rows of the memory cell arrays; a plurality of bit lines connected to the memory cells arrayed in columns of the memory cell arrays; a plurality of dummy cells arrayed in a row direction of the memory cell arrays and are connected to the bit lines; sense amplifiers detecting data within the memory cells by using an average value of electric characteristics of the dummy cells that store mutually different digital data as a reference signal; and a plurality of switching elements electrically connecting four or more of the bit lines in order to generate the reference signal.

    摘要翻译： 本公开涉及一种半导体存储器件，其包括通过累积或放电来存储数据的存储器单元; 具有设置在矩阵中的多个存储单元的存储单元阵列; 连接到排列在存储单元阵列中的存储单元的多个字线; 多个位线连接到存储单元阵列的列中排列的存储单元; 多个虚拟单元排列在存储单元阵列的行方向上并连接到位线; 读出放大器通过使用存储相互不同的数字数据的虚拟单元的电特性的平均值作为参考信号来检测存储单元内的数据; 以及电连接四个或更多个位线以便产生参考信号的多个开关元件。