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11 条记录 (耗时 0.025 秒)

    Thin film capacitor
    1.
    发明授权
    Thin film capacitor 失效
    薄膜电容器

    公开(公告)号：US5889299A

    公开(公告)日：1999-03-30

    申请号：US804394

    申请日：1997-02-21

    申请人： Kazuhide Abe ,  Shuichi Komatsu ,  Mitsuaki Izuha ,  Noburu Fukushima ,  Kenya Sano ,  Takashi Kawakubo

    发明人： Kazuhide Abe ,  Shuichi Komatsu ,  Mitsuaki Izuha ,  Noburu Fukushima ,  Kenya Sano ,  Takashi Kawakubo

    IPC分类号： H01L21/02 ,  H01L29/76

    CPC分类号： H01L28/55

    摘要： A thin film capacitor including a first electrode having on its surface a (100) face of cubic system or a (001) face of tetragonal system, a dielectric thin film epitaxially grown on the first electrode and exhibiting a crystal structure which inherently belongs to a perovskite structure of cubic system, and a second electrode formed on the dielectric thin film. Further, the dielectric thin film meets the following relationship V/V.sub.0 .gtoreq.1.01 where a unit lattice volume of true perovskite crystal structure belonging to the cubic system (lattice constant a.sub.0) is represented by V.sub.0 =a.sub.0.sup.3, and a unit lattice volume (lattice constant a=b.noteq.c) which is strained toward a tetragonal system after the epitaxial growth is represented by V=a.sup.2 c, and also meets the following relationship c/a.gtoreq.1.01 where c/a represents a ratio between a lattice constant "c" in the direction thicknesswise of the film and a lattice constant "a" in the direction parallel with a plane of the film.

    摘要翻译： 一种薄膜电容器，包括在其表面上具有立方体系的（100）面或四方晶系的（001）面的第一电极，在第一电极上外延生长并呈现出固有地属于 立方体的钙钛矿结构，以及形成在电介质薄膜上的第二电极。 此外，电介质薄膜满足以下关系V / V0 / = 1.01，其中属于立方体系的真实钙钛矿晶体结构的单位晶格体积（晶格常数a0）由V0 = a03表示，单位晶格体积 晶格常数a = b NOTEQUAL c），其外延生长后由V = a2c表示为四方晶系，并满足以下关系c / a> / = 1.01其中c / a表示晶格常数 在膜的厚度方向上的“c”和与膜的平面平行的方向上的晶格常数“a”。

    Thin film dielectric device
    2.
    发明授权
    Thin film dielectric device 失效
    薄膜电介质器件

    公开(公告)号：US6060735A

    公开(公告)日：2000-05-09

    申请号：US923123

    申请日：1997-09-04

    申请人： Mitsuaki Izuha ,  Noburu Fukushima ,  Kazuhide Abe

    发明人： Mitsuaki Izuha ,  Noburu Fukushima ,  Kazuhide Abe

    IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L33/00

    CPC分类号： H01L28/75 ,  H01L28/55

    摘要： A thin film dielectric device is disclosed, that comprises a substrate, a lower electrode formed on the substrate and composed of a laminate film having columnar grains that have grown in a vertical to a surface of the substrate, a dielectric thin film formed on the lower electrode and composed of a perovskite oxide, the dielectric thin film being a polycrystalline film having columnar grains that have successively grown from the columnar grains of the lower electrode and that takes over a crystal orientation of the lower electrode, the lattice constant of the lower electrode being matched with the lattice constant of the dielectric thin film at the interface therebetween with the columnar grains, and an upper electrode formed on the dielectric thin film. The lattice matching of the columnar grains solves problems of the increase of the leak current of the thin film dielectric device and the degradation of the dielectric breakdown resistance. In addition, the polycrystalline film having the columnar grains that succeed at the interface of the electrode/dielectric thin film can be properly formed on the semiconductor substrate such as Si substrate. Thus, the thin film dielectric device according to the present invention can be applied to a real LSI circuit and so forth.

    摘要翻译： 公开了一种薄膜电介质器件，其包括：衬底，形成在衬底上的下电极，由具有在垂直于衬底表面生长的柱状晶粒的层压膜构成;电介质薄膜，形成在下层 电极，由钙钛矿氧化物构成，所述电介质薄膜是具有从下部电极的柱状晶粒连续生长并且接受下部电极的晶体取向的柱状晶粒的多晶膜，下部电极的晶格常数 与介电薄膜在与柱状晶粒之间的界面处的晶格常数和形成在电介质薄膜上的上电极匹配。 柱状晶粒的晶格匹配解决了薄膜电介质器件的漏电流增加和介电击穿电阻的劣化的问题。 此外，可以在诸如Si衬底的半导体衬底上适当地形成具有在电极/电介质薄膜的界面处成功的柱状晶粒的多晶膜。 因此，根据本发明的薄膜电介质器件可以应用于真正的LSI电路等。

    Semiconductor device manufacturing method, wiring and semiconductor device
    4.
    发明申请
    Semiconductor device manufacturing method, wiring and semiconductor device 有权
    半导体器件制造方法，布线和半导体器件

    公开(公告)号：US20090203181A1

    公开(公告)日：2009-08-13

    申请号：US12320655

    申请日：2009-01-30

    申请人： Kyoichi Suguro ,  Mitsuaki Izuha

    发明人： Kyoichi Suguro ,  Mitsuaki Izuha

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

    摘要翻译： 在本发明的实施例中，通过热处理形成具有分别引入p型杂质，n型杂质和（p + n）杂质的区域的半导体层作为表面层。 除去这些区域上的杂质偏析层，然后在该区域上形成金属材料膜，并进行热处理，从而在半导体层上形成硅化物膜。 在另一个实施方案中，将杂质引入杂质偏析层中，然后在杂质偏析层上形成金属材料膜，并进行热处理以形成硅化物膜。

    SEMICONDUCTOR DEVICE MANUFACTURING METHOD, WIRING AND SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD, WIRING AND SEMICONDUCTOR DEVICE 有权
    半导体器件制造方法，接线和半导体器件

    公开(公告)号：US20120164811A1

    公开(公告)日：2012-06-28

    申请号：US13340109

    申请日：2011-12-29

    申请人： Kyoichi Suguro ,  Mitsuaki Izuha

    发明人： Kyoichi Suguro ,  Mitsuaki Izuha

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

    摘要翻译： 在本发明的一个实施例中，通过热处理形成具有分别引入p型杂质，n型杂质和（p + n）杂质的区域的半导体层作为表面层。 除去这些区域上的杂质偏析层，然后在该区域上形成金属材料膜，并进行热处理，从而在半导体层上形成硅化物膜。 在另一个实施方案中，将杂质引入杂质偏析层中，然后在杂质偏析层上形成金属材料膜，并进行热处理以形成硅化物膜。

    Semiconductor device manufacturing method, wiring and semiconductor device
    6.
    发明申请
    Semiconductor device manufacturing method, wiring and semiconductor device 审中-公开
    半导体器件制造方法，布线和半导体器件

    公开(公告)号：US20060160315A1

    公开(公告)日：2006-07-20

    申请号：US11318478

    申请日：2005-12-28

    申请人： Kyoichi Suguro ,  Mitsuaki Izuha

    发明人： Kyoichi Suguro ,  Mitsuaki Izuha

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a suicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

    摘要翻译： 在本发明的实施例中，通过热处理形成具有分别引入p型杂质，n型杂质和（p + n）杂质的区域的半导体层作为表面层。 去除这些区域上的杂质偏析层，然后在该区域上形成金属材料膜，并进行热处理，从而在半导体层上形成硅化物膜。 在另一个实施方案中，将杂质引入杂质偏析层中，然后在杂质偏析层上形成金属材料膜，并进行热处理以形成硅化物膜。

    Semiconductor device manufacturing method, wiring and semiconductor device
    10.
    发明授权
    Semiconductor device manufacturing method, wiring and semiconductor device 有权
    半导体器件制造方法，布线和半导体器件

    公开(公告)号：US07879723B2

    公开(公告)日：2011-02-01

    申请号：US12320655

    申请日：2009-01-30

    申请人： Kyoichi Suguro ,  Mitsuaki Izuha

    发明人： Kyoichi Suguro ,  Mitsuaki Izuha

    IPC分类号： H01L21/321 ,  H01L21/3213 ,  H01L21/4763

    CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

    摘要翻译： 在本发明的实施例中，通过热处理形成具有分别引入p型杂质，n型杂质和（p + n）杂质的区域的半导体层作为表面层。 除去这些区域上的杂质偏析层，然后在该区域上形成金属材料膜，并进行热处理，从而在半导体层上形成硅化物膜。 在另一个实施方案中，将杂质引入杂质偏析层中，然后在杂质偏析层上形成金属材料膜，并进行热处理以形成硅化物膜。