公开(公告)号：US06924518B2

公开(公告)日：2005-08-02

申请号：US10743006

申请日：2003-12-23

申请人： Toshihiko Iinuma ,  Ichiro Mizushima ,  Mitsuaki Izuha ,  Kiyotaka Miyano ,  Kyoichi Suguro

发明人： Toshihiko Iinuma ,  Ichiro Mizushima ,  Mitsuaki Izuha ,  Kiyotaka Miyano ,  Kyoichi Suguro

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L29/66477 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

摘要： There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.

摘要翻译： 公开了一种半导体器件，其包括半导体衬底，形成在半导体衬底内以限定有源区的隔离区，在元件区内以从隔离区升高的表面形成的一对杂质扩散区， SiGe膜形成在杂质扩散区域的上表面上，以部分地覆盖杂质扩散区域的侧表面，SiGe膜的Ge浓度在SiGe膜的下表面处比在 SiGe膜，形成在SiGe膜上的金属硅化物层，以及形成在半导体衬底的有源区中的栅电极，栅极绝缘膜插入其间并且具有形成在侧表面上的侧壁绝缘膜。

公开(公告)号：US20050006637A1

公开(公告)日：2005-01-13

申请号：US10743006

申请日：2003-12-23

申请人： Toshihiko Iinuma ,  Ichiro Mizushima ,  Mitsuaki Izuha ,  Kiyotaka Miyano ,  Kyoichi Suguro

发明人： Toshihiko Iinuma ,  Ichiro Mizushima ,  Mitsuaki Izuha ,  Kiyotaka Miyano ,  Kyoichi Suguro

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/66477 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

摘要： There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.

公开(公告)号：US20080224252A1

公开(公告)日：2008-09-18

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

摘要翻译： 在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸， 以防止形成小平面。 随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

公开(公告)号：US06989316B2

公开(公告)日：2006-01-24

申请号：US10406281

申请日：2003-04-04

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L21/20

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

公开(公告)号：US07772671B2

公开(公告)日：2010-08-10

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

摘要翻译： 一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。 突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。 形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。 所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。

公开(公告)号：US06570217B1

公开(公告)日：2003-05-27

申请号：US09296669

申请日：1999-04-22

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

IPC分类号： H01L2926

CPC分类号： H01L29/66583 ,  H01L21/324 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7831 ,  H01L29/78639

摘要： To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.

公开(公告)号：US06893928B2

公开(公告)日：2005-05-17

申请号：US10390046

申请日：2003-03-18

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

IPC分类号： H01L29/78 ,  H01L21/324 ,  H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L29/66583 ,  H01L21/324 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7831 ,  H01L29/78639

摘要： To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.

摘要翻译： 在硅衬底的位于MOS晶体管的沟道区之下的部分提供空腔。

公开(公告)号：US20060225657A1

公开(公告)日：2006-10-12

申请号：US11304653

申请日：2005-12-16

申请人： Ichiro Mizushima ,  Kyoichi Suguro

发明人： Ichiro Mizushima ,  Kyoichi Suguro

IPC分类号： C23C16/00 ,  H01L21/20

CPC分类号： H01L21/3185 ,  C23C16/345 ,  C23C16/403 ,  C23C16/45536 ,  C23C16/482 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31612 ,  H01L21/31645

摘要： An apparatus for depositing a dielectric film includes a first gas introduction line introducing and disconnect a first gas including a compound containing a constituent element of the dielectric film, to a surface of a substrate stored in a reaction chamber, and a second gas introduction line introducing and disconnect a second gas containing one of an oxidizing agent, a reducing agent, and a nitriding agent, to the surface of the substrate. A heating source repeatedly irradiates a pulsed energy having a pulse width of about 0.1 ms to about 100 ms on the substrate. An evacuation system evacuates the first and second gases from the reaction chamber. A control system sequentially and repeatedly executes a cycle including operations of introducing the first gas, introducing the second gas, and irradiating the energy.

摘要翻译： 一种用于沉积电介质膜的设备包括：第一气体引入管线，将包含含有电介质膜的构成元素的化合物的第一气体引入和断开到存储在反应室中的基板的表面，以及引入第二气体导入管线 并将含有氧化剂，还原剂和渗氮剂的第二气体分离到基板的表面。 加热源在衬底上反复照射脉冲宽度为约0.1ms至约100ms的脉冲能量。 排空系统从反应室排出第一和第二气体。 控制系统顺序并重复执行包括引入第一气体，引入第二气体和照射能量的操作的循环。

公开(公告)号：US08476708B2

公开(公告)日：2013-07-02

申请号：US13346888

申请日：2012-01-10

申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1207

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。 存储单元阵列部分形成在半导体衬底上，并且包括存储单元。 半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。 电路部分形成在半导体层上。 半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

公开(公告)号：US07459748B2

公开(公告)日：2008-12-02

申请号：US11549770

申请日：2006-10-16

申请人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

摘要翻译： 半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。