公开(公告)号：US6115319A

公开(公告)日：2000-09-05

申请号：US23880

申请日：1998-02-13

申请人： Yoshitaka Kinoshita ,  Kenji Nishimoto ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Yoshitaka Kinoshita ,  Kenji Nishimoto ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/08 ,  G11C11/401 ,  G11C11/408 ,  G11C8/18

CPC分类号： G11C11/4085 ,  G11C7/1072 ,  G11C8/08

摘要： A bootstrap circuit is provided for a word line selector for setting word lines connected with dynamic memory cells at a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage. The bootstrap circuit generates a bootstrap voltage which is given a difference substantially equal to the threshold voltage of address select MOSFETs with respect to the high level of bit lines connected with the memory cells, and feeds the bootstrap voltage to the selected word lines. The bootstrap circuit is activated in synchronism with a clock signal at a timing corresponding to an action mode designated by a command in an SDRAM before a precharge action, thereby changing the select level of the word lines from the first voltage to the bootstrap voltage.

摘要翻译： 提供了一种用于字线选择器的引导电路，用于将与动态存储单元相连的字线设置在对应于与第二电压对应的第一电压和非选择电平的选择电平。 引导电路产生自举电压，该自举电压相对于与存储器单元连接的高电平位线给予基本上等于地址选择MOSFET的阈值电压的差值，并将自举电压馈送到所选择的字线。 引导电路在与预充电动作之前的SDRAM中由命令指定的动作模式对应的定时与时钟信号同步地激活，从而将字线的选择电平从第一电压改变为自举电压。

公开(公告)号：US5506804A

公开(公告)日：1996-04-09

申请号：US159205

申请日：1993-11-30

申请人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

发明人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

IPC分类号： G11C11/409 ,  G05F3/24 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401

摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

摘要翻译： 提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。 为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。 此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。 读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。 此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

公开(公告)号：US5276648A

公开(公告)日：1994-01-04

申请号：US818274

申请日：1992-01-08

申请人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

发明人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

IPC分类号： G11C11/409 ,  G05F3/24 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401

摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

摘要翻译： 提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。 为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。 此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。 读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。 此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

公开(公告)号：US5150325A

公开(公告)日：1992-09-22

申请号：US496227

申请日：1990-03-20

申请人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

发明人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

IPC分类号： G11C11/409 ,  G05F3/24 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401

摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

摘要翻译： 提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。 为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。 此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。 读信号作为固化信号传输，然后转换为电压信号以提高读取速度。 此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

公开(公告)号：US06335898B2

公开(公告)日：2002-01-01

申请号：US09808943

申请日：2001-03-16

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G11C800

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US06314044B1

公开(公告)日：2001-11-06

申请号：US09594840

申请日：2000-06-15

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1运算的算术电路，以对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

公开(公告)号：US5995439A

公开(公告)日：1999-11-30

申请号：US188367

申请日：1998-11-10

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G06F17/50 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C8/12 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US5978305A

公开(公告)日：1999-11-02

申请号：US165194

申请日：1998-10-02

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C11/401 ,  G11C8/00 ,  G11C8/12 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

公开(公告)号：US6097663A

公开(公告)日：2000-08-01

申请号：US413641

申请日：1999-10-06

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G06F17/50 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C8/12 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US06609236B2

公开(公告)日：2003-08-19

申请号：US09964615

申请日：2001-09-28

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G06F945

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.