公开(公告)号：US06939787B2

公开(公告)日：2005-09-06

申请号：US10962504

申请日：2004-10-13

申请人： Fumio Ohtake ,  Yasushi Akasaka ,  Atsushi Murakoshi ,  Kyoichi Suguro

发明人： Fumio Ohtake ,  Yasushi Akasaka ,  Atsushi Murakoshi ,  Kyoichi Suguro

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/6656 ,  H01L21/28061 ,  H01L21/28247 ,  H01L29/4941

摘要： The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.

摘要翻译： 半导体器件包括彼此间隔开的形成在硅衬底10中的一对杂质扩散区域，以及在栅极绝缘膜12之间形成的一对杂质扩散区域38之间形成在硅衬底10上方的栅电极26。 栅电极26由形成在栅极绝缘膜12上的多晶硅膜16，形成在多晶硅膜16上并具有与多晶硅膜16不连续的晶粒边界的多晶硅膜30，金属氮化物膜20 形成在多晶硅膜30上，金属膜22形成在阻挡金属膜20上。 由此可以减少硼从第一多晶硅膜16朝向金属氮化物膜20的扩散。 因此，能够抑制栅电极26的耗尽。

公开(公告)号：US20050062115A1

公开(公告)日：2005-03-24

申请号：US10962504

申请日：2004-10-13

申请人： Fumio Ohtake ,  Yasushi Akasaka ,  Atsushi Murakoshi ,  Kyoichi Suguro

发明人： Fumio Ohtake ,  Yasushi Akasaka ,  Atsushi Murakoshi ,  Kyoichi Suguro

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/76 ,  H01L21/3205

CPC分类号： H01L29/6656 ,  H01L21/28061 ,  H01L21/28247 ,  H01L29/4941

摘要： The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.

摘要翻译： 半导体器件包括彼此间隔开的形成在硅衬底10中的一对杂质扩散区域，以及在栅极绝缘膜12之间形成的一对杂质扩散区域38之间形成在硅衬底10上方的栅电极26。 栅电极26由形成在栅极绝缘膜12上的多晶硅膜16，形成在多晶硅膜16上并具有与多晶硅膜16不连续的晶粒边界的多晶硅膜30，金属氮化物膜20 形成在多晶硅膜30上的金属膜22和形成在阻挡金属膜20上的金属膜22.由此可以减少硼从第一多晶硅膜16朝向金属氮化物膜20的扩散。 因此，能够抑制栅电极26的耗尽。

公开(公告)号：US07078776B2

公开(公告)日：2006-07-18

申请号：US10867797

申请日：2004-06-16

申请人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

发明人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66583 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.

摘要翻译： 半导体器件具有形成在半导体衬底中并且由于第一半导体区域中包含的第一导电型有源杂质而具有第一导电类型的第一半导体区域，以及形成在第一半导体区域和第一半导体区域之间的第二半导体区域 并且由于第二半导体区域中包含的第二导电型有源杂质而具有第二导电类型。 第二半导体区域包含第一导电型有源杂质，其浓度为零或小于第二半导体区域中所含的第二导电型有源杂质浓度的四分之一。 绝缘膜和导体形成在第二半导体区域上。 在与第二半导体区域的侧面接触的半导体表面处形成第二导电类型的第三和第四半导体区域。 该半导体器件能够抑制净杂质浓度变化以及由短沟道效应或制造变化引起的阈值电压变化。

公开(公告)号：US06770944B2

公开(公告)日：2004-08-03

申请号：US10303806

申请日：2002-11-26

申请人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

发明人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.

摘要翻译： 半导体器件具有形成在半导体衬底中并且由于第一半导体区域中包含的第一导电型有源杂质而具有第一导电类型的第一半导体区域，以及形成在第一半导体区域和第一半导体区域之间的第二半导体区域 并且由于第二半导体区域中包含的第二导电型有源杂质而具有第二导电类型。 第二半导体区域包含浓度为零或小于第二半导体区域中所含的第二导电型有源杂质的浓度的四分之一的第一导电型活性杂质。 绝缘膜和导体形成在第二半导体区域上。 在与第二半导体区域的侧面接触的半导体表面处形成第二导电类型的第三和第四半导体区域。 该半导体器件能够抑制净杂质浓度变化以及由短沟道效应或制造变化引起的阈值电压变化。

公开(公告)号：US5903053A

公开(公告)日：1999-05-11

申请号：US677397

申请日：1996-07-09

申请人： Tadashi Iijima ,  Hisako Ono ,  Kyoichi Suguro ,  Yasushi Akasaka ,  Shinichi Nakamura

发明人： Tadashi Iijima ,  Hisako Ono ,  Kyoichi Suguro ,  Yasushi Akasaka ,  Shinichi Nakamura

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L29/4975 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/495 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device comprising a conductive layer and an amorphous alloy layer formed on the bottom surface of said conductive layer and acting as a barrier layer. The conductive layer is either an electrode layer or a wiring layer. The amorphous alloy layer is made of a matrix phase and microcrystal grains. The matrix phase consists mainly of a Ti--Si--N amorphous alloy. The microcrystal grains are dispersed in the matrix phase, not continuously arranged in the direction of thickness of the amorphous alloy layer.

摘要翻译： 一种半导体器件，包括形成在所述导电层的底表面上并用作阻挡层的导电层和非晶态合金层。 导电层是电极层或布线层。 非晶合金层由基体相和微晶粒构成。 基体相主要由Ti-Si-N非晶合金组成。 微晶粒分散在基体相中，不是沿非晶合金层的厚度方向连续排列。

公开(公告)号：US06875986B1

公开(公告)日：2005-04-05

申请号：US09559345

申请日：2000-04-27

申请人： Atsushi Murakoshi ,  Kyoichi Suguro ,  Katsuya Okumura

发明人： Atsushi Murakoshi ,  Kyoichi Suguro ,  Katsuya Okumura

IPC分类号： H01J27/02 ,  H01J27/08 ,  H01J37/08

CPC分类号： H01J27/08 ,  H01J27/02 ,  H01J2237/08 ,  H01J2237/31701

摘要： According to the ion generation method, ion source material composed of an element of desired ions to be generated and I is heated so that vapor of the compound is generated, and the ions are generated by discharging the vapor. The iodide has no corrosiveness, and can be stably ionized. Further, it hardly reacts with oxygen or water and is safe.

摘要翻译： 根据离子产生方法，由要产生的所需离子的元素组成的离子源材料被加热，使得产生化合物的蒸汽，并且通过排出蒸气产生离子。 碘化物没有腐蚀性，可以稳定地电离。 此外，它几乎不与氧气或水反应并且是安全的。

公开(公告)号：US06693023B2

公开(公告)日：2004-02-17

申请号：US10079490

申请日：2002-02-22

申请人： Atsushi Murakoshi ,  Kyoichi Suguro

发明人： Atsushi Murakoshi ,  Kyoichi Suguro

IPC分类号： H01L2104

CPC分类号： H01J37/3171 ,  H01L21/26513

摘要： In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.

摘要翻译： 在使用具有提取电极和后加速器的离子注入设备的离子注入方法中，通过设定施加电压，将离子从样品的表面均匀地注入浅区域。 的后加速器高于施加电压。 的提取电极。

公开(公告)号：US5656859A

公开(公告)日：1997-08-12

申请号：US622589

申请日：1996-03-26

申请人： Atsushi Murakoshi ,  Masao Iwase ,  Kyoichi Suguro ,  Mitsuo Koike ,  Tadayuki Asaishi

发明人： Atsushi Murakoshi ,  Masao Iwase ,  Kyoichi Suguro ,  Mitsuo Koike ,  Tadayuki Asaishi

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/456 ,  H01L21/28512

摘要： An impurity diffusion surface layer is formed in a surface of a silicon substrate, and an aluminum electrode is arranged in direct contact with the impurity diffusion layer. The surface layer contains Ge as an impurity serving to change the lattice constant in a concentration of at least 1.times.10.sup.21 cm.sup.-1 under a thermal non-equilibrium state. The lattice constant of the surface layer is set higher than that of silicon containing the same concentration of germanium under a thermal equilibrium state. As a result, it is possible to decrease the Schittky barrier height at the contact between the surface layer and the electrode. The surface layer also contains an electrically active boron as an impurity serving to impart carriers in a concentration higher than the critical concentration of solid solution in silicon under a thermal equilibrium state. The presence of Ge permits the carrier mobility within the surface layer higher than that within silicon.

摘要翻译： 在硅衬底的表面上形成杂质扩散表面层，并且铝电极被布置成与杂质扩散层直接接触。 表面层含有Ge作为杂质，用于在热非平衡状态下以至少1×10 21 cm -1的浓度改变晶格常数。 在热平衡状态下，表面层的晶格常数被设定为高于含有相同浓度的锗的硅的晶格常数。 结果，可以降低表面层和电极之间的接触处的Schittky势垒高度。 表面层还含有作为杂质的电活性硼，其用于赋予在热平衡状态下高于硅中的固溶体的临界浓度的载流子。 Ge的存在允许表面层内的载流子迁移率高于硅内的载流子迁移率。

公开(公告)号：US5656820A

公开(公告)日：1997-08-12

申请号：US560029

申请日：1995-11-17

申请人： Atsushi Murakoshi ,  Kyoichi Suguro ,  Tatsuya Hatanaka

发明人： Atsushi Murakoshi ,  Kyoichi Suguro ,  Tatsuya Hatanaka

IPC分类号： C23F4/00 ,  H01J27/02 ,  H01J27/08 ,  H01J27/14 ,  H01J27/16 ,  H01J27/18 ,  H01J37/08 ,  H01J37/317 ,  H01L21/265

CPC分类号： H01J37/32477 ,  H01J27/022 ,  H01J27/08 ,  H01J27/16 ,  H01J2237/08 ,  H01J2237/31701

摘要： An ion generation device includes a chamber in which plasma is generated, a first opening for introducing gas to be ionized by the plasma, and a second opening for irradiating ions generated from the gas. The inner wall of the chamber is coated with metal which is resistant to chemical etching by the ions and radicals.

摘要翻译： 离子产生装置包括其中产生等离子体的室，用于引入待等离子体离子化的气体的第一开口和用于照射由气体产生的离子的第二开口。 室内壁涂有金属，耐金属离子和自由基进行化学蚀刻。

公开(公告)号：US07772671B2

公开(公告)日：2010-08-10

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

摘要翻译： 一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。 突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。 形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。 所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。