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    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4860086A

    公开(公告)日：1989-08-22

    申请号：US26254

    申请日：1987-03-16

    申请人： Tohru Nakamura ,  Masahiko Ogirima ,  Kazuo Nakazato ,  Takao Miyazaki ,  Naoki Yamamoto ,  Minoru Nagata ,  Shojiro Sugaki, deceased

    发明人： Tohru Nakamura ,  Masahiko Ogirima ,  Kazuo Nakazato ,  Takao Miyazaki ,  Naoki Yamamoto ,  Minoru Nagata ,  Shojiro Sugaki, deceased

    IPC分类号： H01L23/485 ,  H01L23/532

    CPC分类号： H01L23/53271 ,  H01L23/485 ,  H01L2924/0002

    摘要： A semiconductor device is constructed so that an insulation film is provided in regions other than a protruding portion of a substrate. A polycrystalline silicon layer and a metal silicide layer are formed over said insulation film to provide a multi-layer structure, and a take-out portion for at least one of the emitter, base, and collector members of a bipolar transistor provided in the mesa region is constituted by a film of this multi-layer structure. By virtue of the use of metal silicide together with the polycrystalline silicon, a very low resistance is achieved which enhances the device's operating speed. Further, the metal silicide is separated from the protruding portion of the substrate by a portion of the polycrystalline silicon to provide a smooth interface with the substrate. This smooth interface significantly reduces crystal defects in the single crystal substrate.

    摘要翻译： 构造半导体器件，使得绝缘膜设置在除了衬底的突出部分之外的区域中。 在所述绝缘膜上形成多晶硅层和金属硅化物层以提供多层结构，以及设置在台面中的双极晶体管的发射极，基极和集电极构件中的至少一个的取出部分 区域由该多层结构的膜构成。 由于金属硅化物与多晶硅一起使用，所以实现了非常低的电阻，这增强了器件的工作速度。 此外，金属硅化物通过多晶硅的一部分与衬底的突出部分分离，以提供与衬底的平滑界面。 这种平滑的界面显着地减少了单晶衬底中的晶体缺陷。

    Radiation resistant bipolar memory
    5.
    发明授权
    Radiation resistant bipolar memory 失效
    耐辐射双极记忆

    公开(公告)号：US4956688A

    公开(公告)日：1990-09-11

    申请号：US374570

    申请日：1989-06-27

    申请人： Noriyuki Honma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

    发明人： Noriyuki Honma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

    IPC分类号： H01L27/102 ,  H01L29/732

    CPC分类号： H01L27/1025 ,  H01L29/7327

    摘要： A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

    摘要翻译： 提供了具有高抗免除由α射线引起的软误差的结构的双极记忆。 触发器的晶体管，即存储单元的基本电路被反转，并且其负载装置具有用于屏蔽触发器与基板内产生的噪声的屏蔽装置。 采用pnp型晶体管或肖特基势垒二极管作为负载器件。 在设置有器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层。 跨越掩埋层和掺杂层施加反向偏压，以切断衬底内产生的噪声。

    Semiconductor device in which electrodes are formed in a self-aligned manner
    6.
    发明授权
    Semiconductor device in which electrodes are formed in a self-aligned manner 失效
    电极以自对准方式形成的半导体器件

    公开(公告)号：US4887145A

    公开(公告)日：1989-12-12

    申请号：US937610

    申请日：1986-12-03

    申请人： Katsuyoshi Washio ,  Tohru Nakamura ,  Kazuo Nakazato ,  Masatada Horiuchi ,  Tetsuya Hayashida

    发明人： Katsuyoshi Washio ,  Tohru Nakamura ,  Kazuo Nakazato ,  Masatada Horiuchi ,  Tetsuya Hayashida

    IPC分类号： H01L21/285 ,  H01L21/32 ,  H01L21/331 ,  H01L29/423 ,  H01L29/732 ,  H01L29/04

    CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/32 ,  H01L29/42304 ,  H01L29/7325

    摘要： A bipolar transistor capable of operating at high speeds. In a bipolar transistor designed for operation at high speeds, a polycrystalline silicon layer used as a base electrode effects is a contact area with respect to the base region which lacks precision or tends to increase. Further, when the transistor is formed in a small size, the ratio of the contact area with respect to the polycrystalline area increases, making it difficult to increase the operation speed. In order to reduce the contact area of the polycrystalline silicon layer, this invention deals with the structure in which the polycrystalline silicon layer is brought into contact with a portion near the edge of the convex semiconductor layer maintaining a small size and a high precision.

    摘要翻译： 能够高速运行的双极晶体管。 在设计用于高速运行的双极晶体管中，用作基极效应的多晶硅层是相对于缺少精度或倾向于增加的基极区域的接触面积。 此外，当晶体管形成为小尺寸时，接触面积相对于多晶面积的比率增加，使得难以提高操作速度。 为了减少多晶硅层的接触面积，本发明涉及多晶硅层与凸半导体层的边缘附近的部分接触的结构，保持小尺寸和高精度。

    Radiation resistant bipolar memory
    7.
    发明授权
    Radiation resistant bipolar memory 失效
    耐辐射双极记忆

    公开(公告)号：US4858184A

    公开(公告)日：1989-08-15

    申请号：US42698

    申请日：1987-04-27

    申请人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

    发明人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

    IPC分类号： G11C11/411

    CPC分类号： G11C11/4113 ,  G11C11/4116

    摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

    摘要翻译： 提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。 触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。 采用双极晶体管和肖特基势垒二极管作为负载器件。 在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂 以切断衬底内产生的噪音。

    Radiation resistant bipolar memory
    10.
    发明授权
    Radiation resistant bipolar memory 失效
    耐辐射双极记忆

    公开(公告)号：US4958320A

    公开(公告)日：1990-09-18

    申请号：US361633

    申请日：1989-06-02

    申请人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

    发明人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

    IPC分类号： G11C11/411 ,  H01L27/102

    CPC分类号： G11C11/4113 ,  G11C11/4116 ,  H01L27/1025

    摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

    摘要翻译： 提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。 触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。 采用双极晶体管和肖特基势垒二极管作为负载器件。 在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂 以切断衬底内产生的噪音。