Method and apparatus for analyzing and designing semiconductor device using calculated surface potential
    2.
    发明授权
    Method and apparatus for analyzing and designing semiconductor device using calculated surface potential 有权
    使用计算的表面电位分析和设计半导体器件的方法和装置

    公开(公告)号:US08219963B2

    公开(公告)日:2012-07-10

    申请号:US12457374

    申请日:2009-06-09

    申请人: Hironori Sakamoto

    发明人: Hironori Sakamoto

    IPC分类号: G06F17/50 G06F7/60 G06F17/10

    CPC分类号: G06F17/5018

    摘要: In a support apparatus for analysis and design of a semiconductor device, a function indicating an impurity concentration distribution in a channel region of a first transistor in a depth direction is set. A structure data indicating a structure of a transistor device and a measurement value of each of electric characteristics of the transistor are related. A Poisson's equation, which is express by using the function, is solved by using a depletion layer width as a variable to calculate a surface potential, and a first calculation value of the electric characteristic of the first transistor is calculated by using the surface potential. A determining section determines the function to indicate the impurity concentration distribution of a first transistor when a measurement value corresponding to a first structure data which indicates a structure of the first transistor, and the first calculation value are substantially coincident with each other.

    摘要翻译: 在用于半导体器件的分析和设计的支持设备中,设置指示在深度方向上的第一晶体管的沟道区域中的杂质浓度分布的函数。 指示晶体管器件的结构的结构数据和晶体管的每个电特性的测量值都相关。 通过使用耗尽层宽度作为变量来计算表面电位,通过使用该函数表示的泊松方程,并且通过使用表面电位来计算第一晶体管的电特性的第一计算值。 当与表示第一晶体管的结构的第一结构数据相对应的测量值和第一计算值基本上一致时,确定部分确定指示第一晶体管的杂质浓度分布的函数。

    Method for analyzing and designing semiconductor device and apparatus for the same
    3.
    发明申请
    Method for analyzing and designing semiconductor device and apparatus for the same 有权
    分析和设计半导体器件及其设备的方法

    公开(公告)号:US20090319966A1

    公开(公告)日:2009-12-24

    申请号:US12457374

    申请日:2009-06-09

    申请人: Hironori Sakamoto

    发明人: Hironori Sakamoto

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5018

    摘要: In a support apparatus for analysis and design of a semiconductor device, a function indicating an impurity concentration distribution in a channel region of a first transistor in a depth direction is set. A structure data indicating a structure of a transistor device and a measurement value of each of electric characteristics of the transistor are related. A Poisson's equation, which is express by using the function, is solved by using a depletion layer width as a variable to calculate a surface potential, and a first calculation value of the electric characteristic of the first transistor is calculated by using the surface potential. A determining section determines the function to indicate the impurity concentration distribution of a first transistor when a measurement value corresponding to a first structure data which indicates a structure of the first transistor, and the first calculation value are substantially coincident with each other, and stores the function in the storage section. The above operations are repeated until the first calculation value and the measurement value are substantially coincident with each other.

    摘要翻译: 在用于半导体器件的分析和设计的支持设备中,设置指示在深度方向上的第一晶体管的沟道区域中的杂质浓度分布的函数。 指示晶体管器件的结构的结构数据和晶体管的每个电特性的测量值都相关。 通过使用耗尽层宽度作为变量来计算表面电位,通过使用该函数表示的泊松方程,并且通过使用表面电位来计算第一晶体管的电特性的第一计算值。 当与表示第一晶体管的结构的第一结构数据相对应的测量值和第一计算值基本上一致时,确定部分确定表示第一晶体管的杂质浓度分布的函数,并且存储 功能在存储部分。 重复上述操作,直到第一计算值和测量值彼此基本一致。

    Method of extracting parameters of diffusion model capable of extracting the parameters quickly
    4.
    发明授权
    Method of extracting parameters of diffusion model capable of extracting the parameters quickly 失效
    提取能够快速提取参数的扩散模型参数的方法

    公开(公告)号:US06577993B1

    公开(公告)日:2003-06-10

    申请号:US09386304

    申请日:1999-08-31

    申请人: Hironori Sakamoto

    发明人: Hironori Sakamoto

    IPC分类号: G06F1750

    CPC分类号: G06F17/5018

    摘要: In a method of extracting parameters of a diffusion model from object parameters to be used in a process simulation of a semiconductor manufacturing process, classifying the object parameters into a first through an N-th (N being a natural integer not smaller than 2) groups, the first group being used for classifying thereinto the most fundamental physical and least model-dependent parameters, the N-th group being used for classifying thereinto the least fundamental physical and most model-dependent parameters, and extracting successively the classified parameters in the first through the N-th groups in the order from the first to the N-th group.

    摘要翻译: 在从半导体制造过程的过程模拟中使用的对象参数提取扩散模型的参数的方法中,将目标参数分为第一至第N(N为不小于2的自然整数)组 第一组被用于分类最基本的物理和最不依赖模型的参数,第N组被用于对其中的最基本的物理和最依赖模型的参数进行分类,并连续地提取第一组中的分类参数 通过N组从第一组到第N组的顺序。

    Circuit simulation apparatus incorporating diffusion length dependence of transistors and method for creating transistor model
    5.
    发明授权
    Circuit simulation apparatus incorporating diffusion length dependence of transistors and method for creating transistor model 失效
    结合晶体管的扩散长度依赖性的电路模拟装置和用于产生晶体管模型的方法

    公开(公告)号:US07222060B2

    公开(公告)日:2007-05-22

    申请号:US10668974

    申请日:2003-09-24

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5036

    摘要: From the data of diffusion-length-dependent parameters extracted from the parameters of the transistor model of MOS transistors and from the parameters of transistors having various diffusion lengths, a diffusion-length-dependent parameter correcting unit creates approximate expressions of the diffusion length dependence of these parameters, and calculates parameter correction values to be used instead of original parameter values by using the created approximate expressions. Hence, the correction values can be used easily instead of the original parameter values, whereby a transistor model of MOS transistors having a different diffusion length DL can be created easily. Circuit simulation in consideration of the diffusion length dependence of the drain currents of MOS transistors can thus be carried out, whereby highly accurate simulation can be attained.

    摘要翻译: 根据从MOS晶体管的晶体管模型的参数和具有各种扩散长度的晶体管的参数提取的扩散长度相关参数的数据,扩散长度相关参数校正单元产生扩散长度依赖性的近似表达式 这些参数,并通过使用创建的近似表达式计算要使用的参数校正值而不是原始参数值。 因此,可以容易地使用校正值而不是原始参数值,由此可以容易地创建具有不同扩散长度DL的MOS晶体管的晶体管模型。 考虑到MOS晶体管的漏极电流的扩散长度依赖性的电路仿真可以进行,从而可以实现高精度的仿真。

    Feed-forward amplifier and controller of the same
    6.
    发明授权
    Feed-forward amplifier and controller of the same 失效
    前馈放大器和控制器相同

    公开(公告)号:US06489844B2

    公开(公告)日:2002-12-03

    申请号:US09735759

    申请日:2000-12-13

    IPC分类号: H03F366

    CPC分类号: H03F1/3235

    摘要: A feed-forward amplifier and a controller thereof. Two types of second pilot signals, sum frequency and difference frequency of a base pilot signal and a local oscillation signal, are generated by an injection-side mixer and injected into a distortion detection loop. Part of a signal appearing at an output terminal is branched, converted in frequency by a detection-side mixer using the local oscillation signal, filtered by a narrow-band filter, input to a synchronizing detector with the filtered output of the filter as error signals, and synchronizing detected with reference to the base pilot signal so as to generate control signals for a distortion rejection loop. The spectrums of the second pilot signals may be spread. A process to cancel the input signal component at the detection side may be performed. A simple circuit configuration enhances the distortion component rejection and suppression effect and shortens the time required until an optimum control state is established.

    摘要翻译: 一种前馈放大器及其控制器。 通过注入侧混频器产生两种类型的第二导频信号,基频导频信号和本地振荡信号的和频和差频,并将其注入到失真检测环路中。 出现在输出端子处的信号的一部分通过检测侧混频器被分频,使用本地振荡信号进行滤波,由窄带滤波器滤波,输入到同步检测器,滤波器的滤波器作为误差信号 并且参考基准导频信号进行同步检测,以产生用于失真抑制环路的控制信号。 可以扩展第二导频信号的频谱。 可以执行消除检测侧的输入信号分量的处理。 简单的电路配置增强了失真分量抑制和抑制效果,缩短了所需的时间,直到建立最佳控制状态。

    FET bias circuit
    7.
    发明授权
    FET bias circuit 失效
    FET偏置电路

    公开(公告)号:US06486724B2

    公开(公告)日:2002-11-26

    申请号:US09773354

    申请日:2001-01-31

    IPC分类号: H03K17687

    摘要: A circuit for biasing an FET, comparing a gate bias voltage of the FET with a reference voltage at an operational amplifier and performing closed-loop control on the gate bias voltage of the FET with the output of the operational amplifier. The temperature characteristics of the mutual conductance of the FET is compensated by setting the temperature characteristics of one or both of two voltage dividing resistors. Variations in a drain bias current due to input signal level and temperature changes can be suppressed. The circuit at the gate and the circuit at the drain are separate, making possible class A, class AB, and class B operations. The voltage drop at the gate resistor can be ignored so that the gate resistor can be designed with priority given to stability of the RF characteristics.

    摘要翻译: 用于偏置FET的电路,将FET的栅极偏置电压与运算放大器的参考电压进行比较,并且利用运算放大器的输出对FET的栅极偏置电压执行闭环控制。 通过设置两个分压电阻中的一个或两个的温度特性来补偿FET的互导的温度特性。 可以抑制由输入信号电平和温度变化引起的漏极偏置电流的变化。 栅极电路和漏极电路分开,使A类,AB类和B类工作成为可能。 可以忽略栅极电阻器处的电压降,从而可以根据RF特性的稳定性优先设计栅极电阻器。

    Method and apparatus of establishing a region to be made amorphous
    8.
    发明授权
    Method and apparatus of establishing a region to be made amorphous 失效
    建立无定形区域的方法和装置

    公开(公告)号:US06212487B1

    公开(公告)日:2001-04-03

    申请号:US09037852

    申请日:1998-03-10

    申请人: Hironori Sakamoto

    发明人: Hironori Sakamoto

    IPC分类号: G06F1750

    CPC分类号: G06F17/5018

    摘要: In a method of accurately determining an area that has been changed to an amorphous state which uses a computer simulation of a semiconductor manufacturing process, the impurity concentration at the crystalline-amorphous boundary is taken as the parameter C. The value obtained by dividing the implanted ion concentration obtained by means of an ion implantation simulator by the parameter Ca is defined as the amorphous conversion ratio parameter, and a region in which this amorphous conversion ratio parameter is 1 or greater is taken to be an area that is converted to an amorphous state.

    摘要翻译: 在使用半导体制造工艺的计算机模拟来精确地确定已经改变为非晶状态的区域的方法中,将结晶非晶界面处的杂质浓度作为参数C。通过将植入 将通过参数Ca的离子注入模拟器获得的离子浓度定义为非晶转化率参数,将该非晶转化率参数为1以上的区域作为转化为非晶态的区域 。

    Control circuit for automatically controlled feed forward nonlinear
distortion compensation amplifier
    9.
    发明授权
    Control circuit for automatically controlled feed forward nonlinear distortion compensation amplifier 失效
    用于自动控制前馈非线性失真补偿放大器的控制电路

    公开(公告)号:US5327096A

    公开(公告)日:1994-07-05

    申请号:US16244

    申请日:1993-02-11

    CPC分类号: H03F1/3229 H03F2201/3212

    摘要: A control circuit for an automatically controlled feed forward nonlinear distortion compensation amplifier. The control circuit controls a distortion detection loop and a distortion removal loop. The distortion detection loop is a loop for feeding forward input to a main amplifier into a first directional coupler. The distortion removal loop is a loop for feeding forward distortion elements into a second directional coupler. The main amplifier is preceded by a variable attenuator and a variable phase shifter. A variable attenuator and a variable phase shifter are also located in a feed forward path to the second directional coupler. The control circuit controls the variable attenuator and the variable phase shifter preceding the main amplifier for detecting the distortion elements. The control circuit controls the variable attenuator and the variable phase shifter located in the feed forward path to the second directional coupler for removing the distortion elements. A temperature compensation signal and an adjustment signal are added to a control signal by each adder provided at the output stage of the control circuit.

    摘要翻译: 一种用于自动控制前馈非线性失真补偿放大器的控制电路。 控制电路控制失真检测环路和失真消除环路。 失真检测环路是用于将主放大器的正向输入馈送到第一定向耦合器的环路。 失真去除环路是用于将前向失真元件馈送到第二定向耦合器的环路。 主放大器之前有可变衰减器和可变移相器。 可变衰减器和可变移相器也位于到第二定向耦合器的前馈路径中。 控制电路控制主放大器之前的可变衰减器和可变移相器,用于检测失真元件。 控制电路控制可变衰减器和位于到第二定向耦合器的前馈路径中的可变移相器以去除失真元件。 通过设置在控制电路的输出级的每个加法器将温度补偿信号和调整信号加到控制信号上。

    Analyzing method of semiconductor device, designing method thereof, and design supporting apparatus
    10.
    发明授权
    Analyzing method of semiconductor device, designing method thereof, and design supporting apparatus 有权
    分析半导体器件的方法,其设计方法和设计支持装置

    公开(公告)号:US08296700B2

    公开(公告)日:2012-10-23

    申请号:US12791535

    申请日:2010-06-01

    申请人: Hironori Sakamoto

    发明人: Hironori Sakamoto

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5036

    摘要: A design supporting apparatus of a semiconductor device, includes sections to perform: setting an impurity concentration with respect to a channel direction and a depth direction to node points arranged discretely in a channel region of a model transistor based on a predetermined concentration distribution rule; calculating an electric characteristic of the model transistor by using the impurity concentration; and storing the impurity concentration as a model parameter of the model transistor in a storage unit, when the calculated electric characteristic and an electric characteristic prepared previously are coincident with each other within a predetermined range. The device characteristic calculating section calculates a surface potential to each of the node points by reducing a dimension of the impurity concentration in the depth direction, corrects the surface potential based on interaction between the node points adjacent to each other, and calculates the electric characteristic by using the corrected surface potential.

    摘要翻译: 一种半导体器件的设计支持装置,包括:基于预定浓度分布规则,将相对于沟道方向和深度方向的杂质浓度设置为离散地设置在模型晶体管的沟道区域中的节点; 通过使用杂质浓度计算模型晶体管的电特性; 以及当预先计算的电特性和电特性在预定范围内彼此一致时,将杂质浓度作为模型晶体管的模型参数存储在存储单元中。 器件特性计算部分通过减小深度方向上的杂质浓度的尺寸来计算每个节点的表面电位,根据彼此相邻的节点之间的相互作用来校正表面电位,并且通过 使用校正后的表面电位。