公开(公告)号：US20120208348A1

公开(公告)日：2012-08-16

申请号：US13454114

申请日：2012-04-24

申请人： Kazuya HANAOKA ,  Hideki TSUYA ,  Masaharu NAGAI

发明人： Kazuya HANAOKA ,  Hideki TSUYA ,  Masaharu NAGAI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.

摘要翻译： 本发明的一个实施方案的方法包括：第一步骤，用离子照射键合衬底，以在接合衬底中形成脆化区; 将所述接合衬底粘合到其上具有绝缘层的基底衬底的第二步骤; 在所述脆化区域分割所述键合衬底以在所述基底衬底上形成半导体层并在其间具有绝缘层的第三步骤; 以及第四步骤，将在脆化区域分裂的键合衬底在氩气氛中进行第一次热处理，然后在氧和氮的混合气氛中进行第二次热处理，以形成再加工的接合衬底。 在第一步中再次使用再处理的键合衬底作为键合衬底。

公开(公告)号：US20100273310A1

公开(公告)日：2010-10-28

申请号：US12762675

申请日：2010-04-19

申请人： Kazuya HANAOKA ,  Hideki TSUYA ,  Masaharu NAGAI

发明人： Kazuya HANAOKA ,  Hideki TSUYA ,  Masaharu NAGAI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.

摘要翻译： 本发明的一个实施方案的方法包括：第一步骤，用离子照射键合衬底，以在接合衬底中形成脆化区; 将所述接合衬底粘合到其上具有绝缘层的基底衬底的第二步骤; 在所述脆化区域分割所述键合衬底以在所述基底衬底上形成半导体层并在其间具有绝缘层的第三步骤; 以及第四步骤，将在脆化区域分裂的键合衬底在氩气氛中进行第一次热处理，然后在氧和氮的混合气氛中进行第二次热处理，以形成再加工的接合衬底。 在第一步中再次使用再处理的键合衬底作为键合衬底。

公开(公告)号：US20130023108A1

公开(公告)日：2013-01-24

申请号：US13551677

申请日：2012-07-18

申请人： Kazuya HANAOKA ,  Yujiro SAKURADA ,  Hideki TSUYA ,  Makoto FURUNO ,  Miku FUJITA

发明人： Kazuya HANAOKA ,  Yujiro SAKURADA ,  Hideki TSUYA ,  Makoto FURUNO ,  Miku FUJITA

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/02238 ,  H01L21/02255

摘要： An insulating layer is formed on a surface of a semiconductor wafer which is to be a bond substrate and an embrittlement region is formed in the semiconductor wafer by irradiation with accelerated ions. Then, a base substrate and the semiconductor wafer are attached to each other. After that, the semiconductor wafer is divided at the embrittlement region by performing heat treatment and an SOI substrate including a semiconductor layer over the base substrate with the insulating layer interposed therebetween is formed. Before the SOI substrate is formed, heat treatment is performed on the semiconductor wafer at a temperature of higher than or equal to 1100° C. under a non-oxidizing atmosphere in which the concentration of impurities is reduced. In this manner, the planarity of the film formed on the semiconductor wafer when heat treatment is performed can be improved.

摘要翻译： 在作为接合衬底的半导体晶片的表面上形成绝缘层，并且通过照射加速离子在半导体晶片中形成脆化区域。 然后，将基底基板和半导体晶片相互连接。 之后，通过进行热处理，将半导体晶片分割在脆化区域，并且形成包含半导体层的SOI基板，并且在基底基板上插入绝缘层。 在形成SOI衬底之前，在杂质浓度降低的非氧化气氛下，在高于或等于1100℃的温度下对半导体晶片进行热处理。 以这种方式，可以提高在进行热处理时在半导体晶片上形成的膜的平面度。

公开(公告)号：US20110183445A1

公开(公告)日：2011-07-28

申请号：US13011355

申请日：2011-01-21

申请人： Kazuya HANAOKA ,  Hideki TSUYA ,  Yoshihiro KOMATSU

发明人： Kazuya HANAOKA ,  Hideki TSUYA ,  Yoshihiro KOMATSU

IPC分类号： H01L21/66 ,  H01L21/78

CPC分类号： H01L21/76254 ,  H01L21/02032 ,  H01L21/3225 ,  H01L22/12 ,  H01L22/20

摘要： An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.

摘要翻译： 在作为接合衬底的半导体晶片的表面上形成绝缘层，并且执行加速离子的照射，从而在晶片内形成脆化区域。 接下来，将该半导体晶片和诸如玻璃基板或半导体晶片的基底基板彼此附接。 然后，通过热处理将半导体晶片分割在脆化区域，由此制造SOI衬底，其中半导体层设置在基底衬底上，绝缘层置于其之间。 在制造该SOI衬底之前，在诸如氩气气氛或氧气和氮气的混合气氛的非氧化性气氛下，在1100℃以上对半导体晶片进行热处理。

公开(公告)号：US20100062583A1

公开(公告)日：2010-03-11

申请号：US12555825

申请日：2009-09-09

申请人： Kazuya HANAOKA ,  Takashi SHINGU ,  Taichi ENDO

发明人： Kazuya HANAOKA ,  Takashi SHINGU ,  Taichi ENDO

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： To provide a manufacturing method of a semiconductor device in which, even when the semiconductor device is formed over an SOI substrate which uses a glass substrate, an insulating film and a semiconductor film over the glass substrate are not peeled by stress applied by a conductive film in formation of the conductive film for forming a gate electrode. A semiconductor device is manufactured by the steps of forming a first insulating film over a bond substrate, forming an embrittlement layer by adding ions from a surface of the bond substrate, bonding the bond substrate to a glass substrate with the first insulating film interposed therebetween, separating the bond substrate along the embrittlement layer to form a semiconductor film over the glass substrate with the first insulating film interposed therebetween, removing a peripheral region of the first insulating film and the semiconductor film to expose part of the glass substrate, forming a gate insulating film over and in contact with the semiconductor film and the glass substrate, and forming a stacked conductive film over and in contact with the gate insulating film, in which the stacked conductive film includes a conductive film having a tensile stress and a conductive film having a compressive stress.

摘要翻译： 为了提供一种半导体器件的制造方法，其中即使半导体器件形成在使用玻璃衬底的SOI衬底上，绝缘膜和玻璃衬底上的半导体膜也不会被导电膜施加的应力剥离 形成用于形成栅电极的导电膜。 通过以下步骤制造半导体器件：通过在接合衬底上形成第一绝缘膜，通过从接合衬底的表面添加离子形成脆化层，将接合衬底与第一绝缘膜接合在玻璃衬底上， 沿着所述脆化层分离所述接合衬底，以在所述玻璃衬底上形成半导体膜，并且在所述玻璃衬底之间插入所述第一绝缘膜，除去所述第一绝缘膜和所述半导体膜的周边区域，以暴露所述玻璃衬底的一部分，形成栅极绝缘 并且与半导体膜和玻璃基板接触并且形成与栅极绝缘膜接触的层叠导电膜，其中层叠导电膜包括具有拉伸应力的导电膜和具有拉伸应力的导电膜 压应力。

公开(公告)号：US20130075732A1

公开(公告)日：2013-03-28

申请号：US13604962

申请日：2012-09-06

申请人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

发明人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.

摘要翻译： 提供具有高电特性的小型化晶体管，其产率高。 在包括晶体管的半导体器件中，实现了高性能，高可靠性和高生产率。 在包括晶体管的半导体器件中，依次堆叠其中设置有侧壁绝缘层的侧表面上的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管，源极和漏极电极层被设置为与 氧化物半导体膜和侧壁绝缘层。 在制造半导体器件的过程中，层叠导电膜和层间绝缘膜以覆盖氧化物半导体膜，侧壁绝缘层和栅极电极层，以及栅极上的层间绝缘膜和导电膜 通过化学机械抛光方法去除层，从而形成源极和漏极电极层。

公开(公告)号：US20120178238A1

公开(公告)日：2012-07-12

申请号：US13341057

申请日：2011-12-30

申请人： Keiichi SEKIGUCHI ,  Kazuya HANAOKA ,  Daigo ITO

发明人： Keiichi SEKIGUCHI ,  Kazuya HANAOKA ,  Daigo ITO

IPC分类号： H01L21/30

CPC分类号： H01L21/02024 ,  H01L21/0206 ,  H01L21/76254 ,  H01L29/78603

摘要： An SOI substrate including a semiconductor layer whose thickness is even is provided. According to a method for manufacturing the SOI substrate, the semiconductor layer is formed over a base substrate. In the method, a first surface of a semiconductor substrate is polished to be planarized; a second surface of the semiconductor substrate which is opposite to the first surface is irradiated with ions, so that an embrittled region is formed in the semiconductor substrate; the second surface is attached to the base substrate, so that the semiconductor substrate is attached to the base substrate; and separation in the embrittled region is performed. The value of 3σ (σ denotes a standard deviation of thickness of the semiconductor layer) is less than or equal to 1.5 nm.

摘要翻译： 提供了包括厚度均匀的半导体层的SOI衬底。 根据SOI基板的制造方法，在基底基板上形成半导体层。 在该方法中，半导体衬底的第一表面被抛光以被平面化; 半导体衬底的与第一表面相对的第二表面被离子照射，从而在半导体衬底中形成脆化区域; 所述第二表面附接到所述基底基板，使得所述半导体基板被附接到所述基底基板; 并进行脆化区域的分离。 3＆sgr的价值 （＆sgr;表示半导体层的厚度的标准偏差）小于或等于1.5nm。

公开(公告)号：US20110086492A1

公开(公告)日：2011-04-14

申请号：US12894860

申请日：2010-09-30

申请人： Hideto OHNUMA ,  Kazuya HANAOKA

发明人： Hideto OHNUMA ,  Kazuya HANAOKA

IPC分类号： H01L21/71

CPC分类号： H01L21/02032 ,  H01L21/02024 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/76254 ,  H01L21/84

摘要： An object of an embodiment of the disclosed invention is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate. A semiconductor substrate is reprocessed in the following manner: etching treatment is performed on a semiconductor substrate in which a step portion including a damaged semiconductor region and an insulating layer exists in a peripheral portion, whereby the insulating layer is removed; etching treatment is performed on the semiconductor substrate with the use of a mixed solution including a substance that oxidizes a semiconductor material included in the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls oxidation speed of the semiconductor material and dissolution speed of the oxidized semiconductor material, whereby the damaged semiconductor region is selectively removed with a non-damaged semiconductor region left; and heat treatment under an atmosphere including hydrogen is performed.

摘要翻译： 所公开的发明的一个实施例的目的是提供一种适于重新处理半导体衬底的方法，该半导体衬底被重新用于制造SOI衬底。 以下列方式对半导体衬底进行再处理：在周边部分存在包括损坏的半导体区域和绝缘层的阶梯部分的半导体衬底上进行蚀刻处理，从而去除绝缘层; 使用包含氧化半导体衬底中所含的半导体材料的物质，溶解氧化半导体材料的物质和控制半导体材料的氧化速度的物质的混合溶液在半导体衬底上进行蚀刻处理，以及 氧化的半导体材料的溶解速度，由此损坏的半导体区域被选择性地去除，其中未损坏的半导体区域留下; 并在包括氢气在内的气氛下进行热处理。

公开(公告)号：US20080252531A1

公开(公告)日：2008-10-16

申请号：US12055918

申请日：2008-03-26

申请人： Kazuya HANAOKA ,  Hideto OHNUMA ,  Teruyuki FUJII

发明人： Kazuya HANAOKA ,  Hideto OHNUMA ,  Teruyuki FUJII

IPC分类号： H01Q9/04

CPC分类号： H01Q1/2208 ,  H01Q9/0407 ,  H01Q23/00

摘要： An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal. Moreover, by the use of nickel nitride as a metal nitride for the base layer of the antenna, poor connection between the antenna and the integrated circuit can be decreased.

摘要翻译： 本发明的目的是为了防止电路元件的电特性在具有集成电路的半导体器件和形成在同一衬底上的天线的铜扩散的不利影响，该天线使用用于天线的铜电镀。 另一个目的是防止由于在具有集成电路的半导体器件中的天线和集成电路之间的连接不良而导致半导体器件的缺陷，并且天线形成在同一衬底上。 在具有形成在一个基板102上的集成电路100和天线101的半导体器件中，当将铜镀层108用于天线101的导体时，可以防止铜扩散到电路元件并降低不利影响 由于铜扩散而导致的电路元件的电特性，因为天线101的基极层107使用预定金属的氮化物膜。 此外，通过使用氮化镍作为天线的基底层的金属氮化物，可以降低天线与集成电路之间的不良连接。

公开(公告)号：US20130011961A1

公开(公告)日：2013-01-10

申请号：US13539907

申请日：2012-07-02

申请人： Akihiro ISHIZUKA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Sho NAGAMATSU

发明人： Akihiro ISHIZUKA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Sho NAGAMATSU

IPC分类号： H01L21/36

CPC分类号： H01L21/02422 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/3105 ,  H01L29/66969 ,  H01L29/78636 ,  H01L29/7869

摘要： An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.

摘要翻译： 目的在于提供具有优异特性的半导体器件，其中沟道层包括具有高结晶度的氧化物半导体。 此外，提供了包括具有改善的平面度的基膜的半导体器件。 在晶体管的基膜上进行CMP处理，在CMP处理之后进行等离子体处理，由此基膜的中心线平均粗糙度Ra75可以小于0.1nm。 在通过等离子体处理和CMP处理的组合获得的具有平坦度的基膜上形成具有高结晶度的氧化物半导体层，从而提高半导体器件的特性。