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    Development assistance for mixed-language sources
    1.
    发明授权
    Development assistance for mixed-language sources 有权
    对混合语言来源的发展援助

    公开(公告)号：US06799718B2

    公开(公告)日：2004-10-05

    申请号：US10193647

    申请日：2002-07-10

    申请人： Ken Chan ,  Hin Boen ,  Peter Johnson ,  Campegius L. Bronkhorst

    发明人： Ken Chan ,  Hin Boen ,  Peter Johnson ,  Campegius L. Bronkhorst

    IPC分类号： G06F1700

    CPC分类号： G06F8/33

    摘要： Development assistance for a program comprising code in more than one language, is provided appropriately for each language in an integrated development environment. The assistance can include syntax highlighting, structure analysis, error reporting, completion assistance and/or context-sensitive help. The language of the subject element of code is determined and the appropriate assistance processes are applied. If the code is in a supplementary language, routines associated with the supplementary language are invoked to provide the assistance. When needed, information from other parts of the program file is provided to determine the appropriate assistance for the element of code.

    摘要翻译： 对于包含多种语言的代码的程序的开发帮助，适用于集成开发环境中的每种语言。 帮助可以包括语法高亮，结构分析，错误报告，完成帮助和/或上下文相关帮助。 确定代码主题元素的语言并应用适当的辅助过程。 如果代码是补充语言，则调用与补充语言相关联的例程以提供帮助。 当需要时，提供来自程序文件其他部分的信息，以确定代码元素的适当帮助。

    Circuits and methods that attenuate coupled noise
    2.
    发明授权
    Circuits and methods that attenuate coupled noise 有权
    衰减耦合噪声的电路和方法

    公开(公告)号：US07518842B2

    公开(公告)日：2009-04-14

    申请号：US10982128

    申请日：2004-11-05

    申请人： David J Pilling ,  James Fox ,  Ken Chan

    发明人： David J Pilling ,  James Fox ,  Ken Chan

    IPC分类号： H02H3/22

    CPC分类号： H01L27/0251 ,  H01L23/50 ,  H01L23/60 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/10253 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Systems and methods of chip design and package implementation for attenuating noise in timing circuits, including phase-locked-loops (PLL) and delay-locked-loops (DLL), are disclosed. Embodiments of the present invention attenuate coupled noise, such as the effects of ground current surges, or power supply noise coupling through electro-static discharge (ESD) structures. In known systems, the ground supplies for the timing circuits are designed with power and ground supplies, separate from the core power and ground; although the ground supplies are connected via common VSSsubstrate, they are separated from pad ring output driver power and ground supplies. In embodiments of the present invention, the PLL or DLL and core supplies are kept separate from the output driver power and ground supplies, providing for improved systems and methods that attenuate the effects of ground current surges from chip output drivers as they switch from logic highs to logic lows.

    摘要翻译： 公开了用于衰减定时电路中的噪声的芯片设计和封装实现的系统和方法，包括锁相环（PLL）和延迟锁定环（DLL）。 本发明的实施例通过静电放电（ESD）结构来衰减耦合噪声，例如接地电流浪涌的影响或电源噪声耦合。 在已知系统中，定时电路的接地电源设计有电源和地电源，与核心电源和地线分开; 虽然接地电源通过公共VSS基板连接，但它们与焊盘环输出驱动器电源和接地电源分开。 在本发明的实施例中，PLL或DLL和核心电源与输出驱动器电源和接地电源保持分开，从而提供改进的系统和方法，其从芯片输出驱动器切换到逻辑高电平时削弱地电流浪涌的影响 到逻辑低点。

    Circuits and methods that attenuate coupled noise
    3.
    发明申请
    Circuits and methods that attenuate coupled noise 有权
    衰减耦合噪声的电路和方法

    公开(公告)号：US20050128664A1

    公开(公告)日：2005-06-16

    申请号：US10982128

    申请日：2004-11-05

    申请人： David Pilling ,  James Fox ,  Ken Chan

    发明人： David Pilling ,  James Fox ,  Ken Chan

    IPC分类号： H01L23/50 ,  H01L23/60 ,  H01L27/02 ,  H02H9/00

    CPC分类号： H01L27/0251 ,  H01L23/50 ,  H01L23/60 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/10253 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Systems and methods of chip design and package implementation for attenuating noise in timing circuits, including phase-locked-loops (PLL) and delay-locked-loops (DLL), are disclosed. Embodiments of the present invention attenuate coupled noise, such as the effects of ground current surges, or power supply noise coupling through electro-static discharge (ESD) structures. In known systems, the ground supplies for the timing circuits are designed with power and ground supplies, separate from the core power and ground; although the ground supplies are connected via common VSSsubstrate, they are separated from pad ring output driver power and ground supplies. In embodiments of the present invention, the PLL or DLL and core supplies are kept separate from the output driver power and ground supplies, providing for improved systems and methods that attenuate the effects of ground current surges from chip output drivers as they switch from logic highs to logic lows.

    摘要翻译： 公开了用于衰减定时电路中的噪声的芯片设计和封装实现的系统和方法，包括锁相环（PLL）和延迟锁定环（DLL）。 本发明的实施例通过静电放电（ESD）结构来衰减耦合噪声，例如接地电流浪涌的影响或电源噪声耦合。 在已知系统中，定时电路的接地电源设计有电源和地电源，与核心电源和地线分开; 虽然接地电源通过公共的SS SS衬底连接，但是它们与焊盘环输出驱动器电源和接地电源分离。 在本发明的实施例中，PLL或DLL和核心电源与输出驱动器电源和接地电源保持分开，从而提供改进的系统和方法，其从芯片输出驱动器切换到逻辑高电平时削弱地电流浪涌的影响 到逻辑低点。

    System and method for monitoring performance, analyzing capacity and utilization, and planning capacity for networks and intelligent, network connected processes
    6.
    发明授权
    System and method for monitoring performance, analyzing capacity and utilization, and planning capacity for networks and intelligent, network connected processes 有权
    用于监控性能的系统和方法，分析容量和利用率，以及规划网络和智能网络连接进程的能力

    公开(公告)号：US06885641B1

    公开(公告)日：2005-04-26

    申请号：US09452403

    申请日：1999-12-01

    申请人： Ken Chan ,  Fredrick K. P. Klassen ,  Robert M. Silverman

    发明人： Ken Chan ,  Fredrick K. P. Klassen ,  Robert M. Silverman

    IPC分类号： H04L12/24 ,  H04L12/26

    CPC分类号： H04L41/142 ,  H04L43/0852 ,  H04L43/0882 ,  H04L43/0888 ,  H04L43/50

    摘要： Analysis of networks and testing and analyzing intelligent, network connected devices. An instantaneous network utilization value is assigned for the worst surviving ping instance of between 90% and 99% (determined proportionately from the ratio of dropped test samples to surviving test samples), and then used to solve for average network message size and average utilization of the network. A plurality transactions of different types are transmitted across the network to intelligent end systems and the results mathematically evaluated to determine the portion of the total response time contributed by the network and by the end processors; the utilization of the end processor processing subsystems and of the end processor I/O subsystems; and the utilization of the end system as a whole; and of the network and end processors considered as a unitary entity. Steps include determining utilization of the network when test packets are dropped by the network; utilization of intelligent processor and other devices attached to the network when test transactions are dropped, and when not dropped; and response time for remote processes at both the network and processor level.

    摘要翻译： 分析网络，测试和分析智能网络连接设备。 为最坏的幸存ping实例分配了90％到99％之间的瞬时网络利用率（根据从测试样本下降到生存测试样本的比例确定），然后用于解决平均网络消息大小和平均利用率 网络。 不同类型的多个事务通过网络传输到智能终端系统，并且数学评估结果以确定由网络和终端处理器贡献的总响应时间的部分; 最终处理器处理子系统和终端处理器I / O子系统的利用; 和整个终端系统的利用; 并将网络和最终处理器视为一体化实体。 步骤包括在网络丢弃测试数据包时确定网络的利用率; 使用智能处理器和附件到网络的其他设备，当测试交易丢弃时，何时不掉线; 以及在网络和处理器级别的远程进程的响应时间。

    Stopwatch
    9.
    外观设计
    Stopwatch 失效
    跑表

    公开(公告)号：USD439170S1

    公开(公告)日：2001-03-20

    申请号：US29123441

    申请日：2000-05-18

    申请人： Ken Chan

    设计人： Ken Chan

    Method for blocking contamination and stabilizing chip capacitor during attachment using a tape strip
    10.
    发明授权
    Method for blocking contamination and stabilizing chip capacitor during attachment using a tape strip 失效
    在使用带条附着时阻止污染和稳定芯片电容器的方法

    公开(公告)号：US5529957A

    公开(公告)日：1996-06-25

    申请号：US417633

    申请日：1995-04-06

    申请人： Ken Chan

    发明人： Ken Chan

    IPC分类号： H01L23/64 ,  H05K1/02 ,  H05K3/30 ,  H01L21/71 ,  H01L21/764

    CPC分类号： H01L23/642 ,  H05K3/303 ,  H05K3/305 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10636 ,  H05K2203/0191 ,  H05K2203/0769 ,  Y02P70/611 ,  Y02P70/613 ,  Y10S148/014

    摘要： Chip capacitors are attached to an integrated circuit package. Strips of synthetic tape are placed between pairs of chip capacitor pads on the integrated circuit package. The strips of synthetic tape each have a height extending above height of the pairs of chip capacitor pads. In the preferred embodiment, the strips of synthetic tape are strips of polyimide tape. The height of the strips of synthetic tape is selected so that the chip capacitors will be installed at a sufficient distance from the integrated circuit package so that solder balls will not be of sufficient diameter to wedge between the integrated circuit package and the chip capacitors. The chip capacitors are installed over the pairs of chip capacitor pads. The chip capacitors rest on the strips of synthetic tape. For example, the chip capacitors are permanently attached to the pairs of chip capacitors using a solder process. A reflow solder process is then performed. Afterwards, the strips of synthetic tape are removed from the integrated circuit package. After removal of the strips of synthetic tape, a cleaning of area under the chip capacitors may be performed to remove any material under and around the chip capacitors.

    摘要翻译： 芯片电容器连接到集成电路封装。 合成胶带条放置在集成电路封装上的芯片电容器垫对之间。 合成胶带的每条带都具有高于成对的芯片电容器垫的高度的高度。 在优选实施例中，合成带的条带是聚酰亚胺胶带条。 选择合成胶带条的高度，使得片状电容器将安装在与集成电路封装件足够的距离处，使得焊球不会具有足够的直径以楔住集成电路封装和芯片电容器之间。 芯片电容器安装在成对的芯片电容器焊盘上。 贴片电容器放在合成胶带上。 例如，使用焊接工艺将芯片电容器永久地附接到成对的芯片电容器。 然后进行回流焊接工艺。 之后，从集成电路封装中取出合成胶带条。 在去除合成胶带条之后，可以对芯片电容器下的区域进行清洁以去除芯片电容器下面和周围的任何材料。