公开(公告)号：US08160781B2

公开(公告)日：2012-04-17

申请号：US11072494

申请日：2005-03-07

申请人： Ken Naono ,  Masaaki Shimizu ,  Fumio Arakawa ,  Nobuyasu Kanekawa ,  Kohei Sakurai ,  Masatoshi Hoshino ,  Kentaro Yoshimura

发明人： Ken Naono ,  Masaaki Shimizu ,  Fumio Arakawa ,  Nobuyasu Kanekawa ,  Kohei Sakurai ,  Masatoshi Hoshino ,  Kentaro Yoshimura

IPC分类号： B62D6/00

CPC分类号： G05B13/024

摘要： A vehicular control system which includes a user parameter input module, an external parameter input module, a plurality of objective functions, a policy setting module, and a policy node. The user parameter input module Inputs a user parameter. The external parameter input module inputs an external parameter resulting from an outside environment. The objective functions are set for each control characteristic, respectively, so as to calculate an internal parameter of each control target from the user parameter and the external parameter. The policy setting module sets policies indicating a control index of the user for the objective functions respectively. The policy node weights the objective functions on the basis of the policies, adjusts the internal parameter in accordance with the policy so that the internal parameter is optimized among the objective functions, and issues a command to a control node corresponding to the internal parameter.

摘要翻译： 一种车辆控制系统，其包括用户参数输入模块，外部参数输入模块，多个目标功能，策略设置模块和策略节点。 用户参数输入模块输入用户参数。 外部参数输入模块输入外部环境引起的外部参数。 分别为每个控制特性设定目标函数，以根据用户参数和外部参数计算每个控制目标的内部参数。 策略设置模块分别针对目标函数设置指示用户的控制索引的策略。 策略节点根据策略对目标函数加权，根据策略调整内部参数，使内部参数在目标函数之间进行优化，并向与内部参数对应的控制节点发出命令。

公开(公告)号：US20050267663A1

公开(公告)日：2005-12-01

申请号：US11072494

申请日：2005-03-07

申请人： Ken Naono ,  Masaaki Shimizu ,  Fumio Arakawa ,  Nobuyasu Kanekawa ,  Kohei Sakurai ,  Masatoshi Hoshino ,  Kentaro Yoshimura

发明人： Ken Naono ,  Masaaki Shimizu ,  Fumio Arakawa ,  Nobuyasu Kanekawa ,  Kohei Sakurai ,  Masatoshi Hoshino ,  Kentaro Yoshimura

IPC分类号： B60R16/02 ,  B60W10/00 ,  B60W10/02 ,  B60W10/04 ,  B60W10/06 ,  B60W10/10 ,  B60W10/12 ,  B60W10/18 ,  B60W10/184 ,  B60W10/20 ,  B60W10/22 ,  F02D45/00 ,  G05B13/02 ,  G06F17/00

CPC分类号： G05B13/024

摘要： To reduce the man-hour required in tuning control parameters, a vehicular control system of this invention comprises a user parameter input module, an external parameter input module, a plurality of objective functions, a policy setting module, and a policy node. The user parameter input module inputs a user parameter corresponding to an operation of a user. The external parameter input module inputs an external parameter resulting from an outside environment. The objective functions are set for each control characteristic respectively so as to calculate an internal parameter of each control target from the user parameter and the external parameter. The policy setting module sets policies indicating a control index of the user for the objective functions respectively. The policy node weights the objective functions on the basis of the policies, adjusts the internal parameter in accordance with the policy so that the internal parameter is optimized (minimized or maximized) among the objective functions, and issues a command to a control node corresponding to the internal parameter.

摘要翻译： 为了减少调谐控制参数所需的工时，本发明的车辆控制系统包括用户参数输入模块，外部参数输入模块，多个目标功能，策略设置模块和策略节点。 用户参数输入模块输入与用户的操作对应的用户参数。 外部参数输入模块输入外部环境引起的外部参数。 分别为每个控制特性设定目标函数，以从用户参数和外部参数计算每个控制目标的内部参数。 策略设置模块分别针对目标函数设置指示用户的控制索引的策略。 策略节点根据策略对目标函数进行加权，根据策略调整内部参数，使内部参数在目标函数中进行优化（最小化或最大化），并向对应的控制节点发出命令 内部参数。

公开(公告)号：US08402254B2

公开(公告)日：2013-03-19

申请号：US12369075

申请日：2009-02-11

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F9/302

CPC分类号： G06F9/30185 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/3865

摘要： The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.

摘要翻译： RISC数据处理器基于以下思想：在存在许多标志生成指令的情况下，由每个指令产生的标志数量增加，使得标志生成指令的减少超过了数量上的标志使用指令的增加 ，从而实现指令的减少。 使用数据处理器，定义根据操作数的数据大小生成标志的指令。 对于由RISC数据处理器处理的指令集，指令能够执行对多于一个数据大小的操作数的操作，该指令执行与对小数位操作数的小位操作数进行的操作处理相同的处理 并且生成能够应对各个数据大小的标志，而不管添加了经过操作的每个操作数的数据大小。 因此，可以实现RISC数据处理器在指令代码空间紧缩的指令代码空间的减少。

公开(公告)号：US06978460B2

公开(公告)日：2005-12-20

申请号：US10022533

申请日：2001-12-20

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/00

CPC分类号： G06F9/3009 ,  G06F9/30087 ,  G06F9/325 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857

摘要： A time multiplex changing function for priorities among threads is added to a multi-thread processor, and capability for large-scale out-of-order execution is achieved by confining the flows of data among threads, prescribing the execution order in the flow sequence, and executing a plurality of threads having data dependency either simultaneously or in time multiplex.

摘要翻译： 用于线程中的优先级的时间复用改变功能被添加到多线程处理器，并且通过限制线程中的数据流来限制流程序列中的执行顺序来实现大规模无序执行的能力， 并且执行同时或时间复用的具有数据依赖性的多个线程。

公开(公告)号：US06738890B2

公开(公告)日：2004-05-18

申请号：US10145761

申请日：2002-05-16

申请人： Makoto Ishikawa ,  Fumio Arakawa

发明人： Makoto Ishikawa ,  Fumio Arakawa

IPC分类号： G06F1200

CPC分类号： G06F9/383 ,  G06F9/342 ,  G06F12/06 ,  G06F12/0846 ,  G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

摘要： In a memory access process, by identifying the types of memories that can be activated without reducing operating speed and by reducing power consumption, a data processor capable of operating at a high memory-accessing speed is provided. Because memory types can often be differentiated based only on partial bits of the address obtained by addition, a partial bit adder and decision logic are used to make this differentiation at high speed. Because the partial addition preferably does not take into account the possible carry from the lower bits, two types of memories are chosen from memories and are both operated in case the carry should be “1” and in case it should be “0.” The result is chosen by a multiplexor and is output. A determination of the entry address of the memory may be similarly carried out by dividing the memory into odd and even entry number banks and utilizing a partial bit adder. Then, both banks may be activated with the results of the partial bit adder as entries, and one of the results is chosen for output.

公开(公告)号：US6092172A

公开(公告)日：2000-07-18

申请号：US950668

申请日：1997-10-15

申请人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

发明人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

摘要翻译： 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

公开(公告)号：US6038582A

公开(公告)日：2000-03-14

申请号：US950664

申请日：1997-10-15

申请人： Fumio Arakawa ,  Norio Nakagawa ,  Tetsuya Yamada ,  Yonetaro Totsuka

发明人： Fumio Arakawa ,  Norio Nakagawa ,  Tetsuya Yamada ,  Yonetaro Totsuka

IPC分类号： G06F7/38 ,  G06F7/487 ,  G06F7/50 ,  G06F7/509 ,  G06F7/53 ,  G06F7/544 ,  G06F7/548 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F17/10 ,  G06T1/20 ,  G06F7/42

CPC分类号： G06F7/509 ,  G06F7/5443 ,  G06F7/548 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3885 ,  G06F9/3887 ,  G06F7/483

摘要： A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.

摘要翻译： 数据处理器包括并入浮点单元中的算术部分，其中运算部分包括多个乘法器，从分别不同的数据输入信号线组提供浮点数的尾数部分，并执行所提供的尾数部分的相乘;对准器 接收相应乘法器的输出并执行对准移位，指数处理部分，用于基于产生浮点数的指数部分，产生对准器的对准偏移量和归一化前的指数，多输入加法器和指数 在正常化之前，以高速和高精度降低电路的尺寸并且以浮点数进行内部产品操作等。

公开(公告)号：US08402256B2

公开(公告)日：2013-03-19

申请号：US12546809

申请日：2009-08-25

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F9/38

CPC分类号： G06F9/30181 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3867

摘要： The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an instruction of each instruction code type other than a prefix on the basis of a determination result of decoders for determining an instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant to instruction executing means. When an instruction of a target instruction code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target instruction code type as prefix code candidates. When an instruction of a target instruction code type cannot be detected at the rear end of the instruction units to be searched, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target instruction code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head.

摘要翻译： 本发明旨在实现包括具有前缀的指令的指令集中的超标量指令的有效问题。 使用电路，其基于用于确定指令代码类型的解码器的确定结果检索除了前缀之外的每个指令代码类型的指令，将紧接在前的指令与检索到的指令相加，并将结果输出到执行指令 手段。 当在要搜索的多个指令单元中检测到目标指令代码类型的指令时，电路将检测到的指令代码和除目标指令代码类型之外的紧接在前的指令输出作为前缀代码候选。 当在要搜索的指令单元的后端不能检测到目标指令代码类型的指令时，该电路将后端的指令输出为前缀代码候选。 当在指令代码搜索中的头部检测到目标指令代码类型的指令时，电路在头部输出指令代码。

公开(公告)号：US20090282213A1

公开(公告)日：2009-11-12

申请号：US12505128

申请日：2009-07-17

申请人： Hiroshi TANAKA ,  Yohei Akita ,  Tetsuro Honmura ,  Fumio Arakawa ,  Takanobu Tsunoda

发明人： Hiroshi TANAKA ,  Yohei Akita ,  Tetsuro Honmura ,  Fumio Arakawa ,  Takanobu Tsunoda

IPC分类号： G06F15/80 ,  G06F9/02

CPC分类号： H03K19/17752 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

摘要翻译： 能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。 该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径 切换OSW。 包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持 从多个数据输入节点中的任何一个输入的数据。

公开(公告)号：US07328355B2

公开(公告)日：2008-02-05

申请号：US10933292

申请日：2004-09-03

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/171

摘要： The disclosure describes a semiconductor device having a plurality of modules each enabled to perform properly while managing allowable power for an entire chip through distributed power control. A predetermined allowable power consumption value is defined for each module. The predetermined power consumption value refers to power consumption defined taking into account allowable power values for a plurality of modules. Each module takes a difference between the predetermined allowable power consumption value and an actual power consumption value as extra power and notifies other modules of the extra power thereof. To avoid a deadlock, each module is designed to be capable of performing data processing below the predetermined power consumption value without using extra power from another module. When notified of extra power by another module, each module can use for data processing power equal to the predetermined power consumption thereof and the extra power.

摘要翻译： 本公开描述了具有多个模块的半导体器件，每个模块能够通过分布式功率控制来管理整个芯片的允许功率，从而能够正常地执行。 为每个模块定义预定的允许功耗值。 预定功耗值是指考虑到多个模块的可允许功率值而定义的功耗。 每个模块将预定容许功耗值和实际功耗值作为额外功率的差异，并通知其他模块其额外功率。 为了避免死锁，每个模块被设计为能够在不使用来自另一个模块的额外功率的情况下执行低于预定功耗值的数据处理。 当被另一个模块通知额外功率时，每个模块可以使用等于其预定功率消耗的数据处理能力和额外功率。