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21 条记录 (耗时 0.026 秒)

    Magnetic disk storage apparatus
    3.
    发明授权
    Magnetic disk storage apparatus 失效
    磁盘存储装置

    公开(公告)号：US06266200B1

    公开(公告)日：2001-07-24

    申请号：US09438510

    申请日：1999-11-12

    申请人： Kenichi Hase ,  Syoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima ,  Akihiko Hirano ,  Akira Uragami

    发明人： Kenichi Hase ,  Syoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima ,  Akihiko Hirano ,  Akira Uragami

    IPC分类号： G11B509

    CPC分类号： H03L7/093 ,  G11B5/012 ,  G11B20/1403 ,  G11B2020/10916 ,  H03K3/2821 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/095 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06 ,  H04L7/033

    摘要： A magnetic disk storage apparatus having a magnetic disk-type storage medium; a head for reading data recorded on the magnetic disk-type storage medium, a processor, a phase synchronizing circuit having a controllable response characteristic and for outputting a clock signal to handle the data read from the magnetic disk-type storage medium, and a memory for storing information to control the response characteristic of the phase synchronizing circuit previously set in accordance with an access position on the magnetic disk-type storage medium. The processor generates the access position on the magnetic disk-type storage medium and data for commanding the control of the response characteristic of the phase synchronizing circuit in accordance with the information stored in the memory, and commands the control of the response characteristic by the data for the command, at a time consistent with a time of a seek operation of the head for the access position on the magnetic disk-type storage medium or a time before the seek operation of the head. Further, the response characteristic is controlled by the command.

    摘要翻译： 一种具有磁盘式存储介质的磁盘存储装置; 用于读取记录在磁盘式存储介质上的数据的磁头，处理器，具有可控响应特性的相位同步电路，以及用于输出时钟信号以处理从磁盘式存储介质读取的数据的存储器 用于存储用于控制根据磁盘式存储介质上的存取位置预先设定的相位同步电路的响应特性的信息。 处理器根据存储在存储器中的信息产生磁盘式存储介质上的访问位置和用于指示相位同步电路的响应特性的控制的数据，并且通过数据命令对响应特性的控制 在与磁盘式存储介质上的访问位置的头部的寻道操作的时间或头部的搜索操作之前的时间相一致的时间。 此外，响应特性由命令控制。

    Sync data introduction method and system
    5.
    发明授权
    Sync data introduction method and system 失效
    同步数据介绍方法和系统

    公开(公告)号：US5475715A

    公开(公告)日：1995-12-12

    申请号：US886860

    申请日：1992-05-22

    申请人： Kenichi Hase ,  Syoichi Miyazawa ,  Ryutaro Horita ,  Akihiko Hirano ,  Hiroshi Kimura ,  Akira Uragami

    发明人： Kenichi Hase ,  Syoichi Miyazawa ,  Ryutaro Horita ,  Akihiko Hirano ,  Hiroshi Kimura ,  Akira Uragami

    IPC分类号： G11B20/10 ,  G11B20/14 ,  H04L1/00 ,  H04L7/00 ,  H04L7/033 ,  H04L7/08

    CPC分类号： G11B20/1403 ,  H04L7/08 ,  H04L7/033

    摘要： A data device for introducing the data read from a recording medium includes first creation device for receiving a read code signal corresponding to the data stored on a data recording medium to create first two phase signals which repeat inversion with a substantially equal period to each other on the basis of a change in the waveform of the read code; second creation device for receiving the first two phase signals to create second two phase signals with their one phase occupying most of their period having an overlapping portion with each other, the period being twice as long as that of the first two phase signals; and third creation device for receiving the read code signal and said second two phase signals to create a second code signal corresponding to the read code signal which shifts during the one phase period of said second two phase signals. The second two phase signals serve to extend sufficiently the window for introducing the read code to provide stabilized read for the data including jitter due to rotation fluctuation of the recording medium.

    摘要翻译： 用于引入从记录介质读取的数据的数据设备包括：第一创建设备，用于接收与存储在数据记录介质上的数据相对应的读取代码信号，以产生以两个相同周期重复反相的第一两个相位信号 读取代码的波形变化的基础; 第二创建装置，用于接收前两个相位信号以产生第二两相信号，其相位占据其大部分周期具有彼此重叠的部分，该周期是前两个相位信号的两倍; 以及第三创建装置，用于接收读取代码信号和所述第二两个相位信号，以产生对应于在所述第二两个相位信号的一个相位周期期间移位的读取代码信号的第二代码信号。 第二个两个相位信号充分地延伸用于引入读取代码的窗口，以提供包括由记录介质的旋转波动引起的抖动的数据的稳定读数。

    Magnetic disk system and waveform equalizer therefor
    6.
    发明授权
    Magnetic disk system and waveform equalizer therefor 失效
    磁盘系统及其波形均衡器

    公开(公告)号：US5463504A

    公开(公告)日：1995-10-31

    申请号：US62770

    申请日：1993-05-18

    申请人： Hiroshi Kimura ,  Shoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Akihiko Hirano ,  Akira Uragami

    发明人： Hiroshi Kimura ,  Shoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Akihiko Hirano ,  Akira Uragami

    IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14

    CPC分类号： G11B20/10046 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/1403 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1258

    摘要： A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled. Consequently, the delay characteristic is not affected by disparity of circuit components of the transversal circuit, and the write clock frequency and the delay time of the transversal circuit can be set to intended values by merely changing the value stored in the register in response to a variation of the data transfer rate.

    摘要翻译： 根据磁盘上的轨道位置以不同的数据传输速率记录和再现磁盘上的数据的磁盘系统包括对读出波形实现最佳波形整形的横向波形均衡电路。 波形均衡电路由寄存器，频率合成器，PLL和横向电路组成。 横向电路由可变延迟电路，可变增益放大器和加法器组成。 频率合成器产生具有对应于存储在寄存器中的取决于数据传输速率的值的频率的写时钟信号，并且PLL响应于写时钟信号以产生控制信号，通过该控制信号，横向延迟时间 电路被控制。 因此，延迟特性不受横向电路的电路部件的不均匀影响，并且横向电路的写入时钟频率和延迟时间可以通过仅响应于一个变化来改变存储在寄存器中的值来设置为预期值 数据传输速率的变化。

    Address mark generating method and its circuit in a data memory
    7.
    发明授权
    Address mark generating method and its circuit in a data memory 失效
    地址标记生成方法及其在数据存储器中的电路

    公开(公告)号：US5062011A

    公开(公告)日：1991-10-29

    申请号：US327757

    申请日：1989-03-23

    申请人： Kenichi Hase ,  Shyoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima ,  Akira Uragami ,  Takashi Watanabe ,  Yoshinori Yoshino

    发明人： Kenichi Hase ,  Shyoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima ,  Akira Uragami ,  Takashi Watanabe ,  Yoshinori Yoshino

    IPC分类号： G11B20/10 ,  G11B20/14 ,  G11B27/30

    CPC分类号： G11B27/3027 ,  G11B20/1419 ,  G11B20/1426

    摘要： When data are memorized in a 2-7 RLL code on a disc shaped memorizing medium using a sector format, as an address mark in each sector a 2-7 illegal pattern is used; a 1-byte data "8B" in an NRZ signal is converted into a 2-7 RLL code, and further it is modified into the 2-7 illegal pattern.A disc controller in a disc memory inserts the 1-byte data "8B" into a specified position in an NRZ signal and transmits it to an encoder/decoder. In the encoder, the 1-byte data "8B" in an NRZ signal is detected, and a 2-7 illegal pattern is formed by reversing a specified bit of a 2-7 RLL code formed by converting the 1-byte data "8B", and the illegal pattern is sent to the read/write amplifier.

    摘要翻译： 当使用扇区格式将数据存储在盘形存储介质上的2-7 RLL代码中时，作为每个扇区中的地址标记，使用2-7非法模式; NRZ信号中的1字节数据“8B”被转换为2-7 RLL码，并进一步修改为2-7非法码型。 盘存储器中的盘控制器将1字节数据“8B”插入NRZ信号中的指定位置并将其发送到编码器/解码器。 在编码器中，检测到NRZ信号中的1字节数据“8B”，并且通过将通过转换1字节数据“8B”形成的2-7 RLL码的指定位反转来形成2-7非法模式 “，并且非法模式被发送到读/写放大器。

    Disk recording apparatus with adaptive window adjusting
    8.
    发明授权
    Disk recording apparatus with adaptive window adjusting 失效
    具有自适应窗口调节的磁盘记录装置

    公开(公告)号：US5559645A

    公开(公告)日：1996-09-24

    申请号：US216606

    申请日：1994-03-23

    申请人： Shyoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Satoshi Kawamura ,  Shinichi Kojima ,  Toshiyuki Iseki

    发明人： Shyoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Satoshi Kawamura ,  Shinichi Kojima ,  Toshiyuki Iseki

    IPC分类号： G11B5/012 ,  G11B7/0045 ,  G11B20/10 ,  G11B20/14 ,  G11B5/09

    CPC分类号： G11B20/10212 ,  G11B20/1403 ,  G11B5/012 ,  G11B7/0045

    摘要： In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.

    摘要翻译： 在用于在盘装置的盘形记录介质上写入/读取数据的信号处理单元中，数据分离器，代码解码器电路，代码编码器和写补偿电路全部构成在单片机 集成电路。 数据分离器将同步时钟与从盘再现的代码数据分离。 码解码器电路从数据分离器产生来自同步时钟的解码数据，并产生同步的代码数据。 代码编码器将从主计算机或磁盘控制器提供的数据编码为代码数据。 写补偿电路相对于写代码数据补偿峰移。 该集成电路由双极CMOS工艺制造，双极晶体管和CMOS晶体管彼此混合。

    Semiconductor integrated circuit which performs phase synchronization
    9.
    发明授权
    Semiconductor integrated circuit which performs phase synchronization 失效
    执行相位同步的半导体集成电路

    公开(公告)号：US5222002A

    公开(公告)日：1993-06-22

    申请号：US687638

    申请日：1991-04-19

    申请人： Kenichi Hase ,  Shoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima

    发明人： Kenichi Hase ,  Shoichi Miyazawa ,  Ryutaro Horita ,  Shinichi Kojima

    IPC分类号： G11B20/14 ,  G11B5/012 ,  G11B20/10 ,  H03L7/06 ,  H04L25/02 ,  H04L25/45

    CPC分类号： H04L25/0286 ,  G11B20/10009 ,  H04L25/45 ,  G11B5/012 ,  H04L25/0292

    摘要： Pulse detector and a data separator are integrated on a single chip semiconductor integrated circuit. In the pulse detector, an input stage of a gain variable amplifier, which amplifies an input signal applied thereto so as to have a constant peak, includes a bipolar transistor, and a pulse generator for generating a pulse shape signal according to a differential value of an output from the gain variable amplifier includes a Bi-CMOS gate or a CMOS gate. In the data separator, a voltage controlled oscillator for generating a clock signal includes a bipolar transistor. A frequency phase comparator for comparing the pulse shape signal in phases with the clock signal generated by the voltage controlled oscillator to obtain a phase difference, includes a Bi-CMOS gate and a CMOS gate.

    摘要翻译： 脉冲检测器和数据分离器集成在单芯片半导体集成电路上。 在脉冲检测器中，增益可变放大器的输入级放大施加到其上的具有恒定峰值的输入信号，包括双极型晶体管和脉冲发生器，用于根据微分值产生脉冲形状信号 来自增益可变放大器的输出包括Bi-CMOS栅极或CMOS栅极。 在数据分离器中，用于产生时钟信号的压控振荡器包括双极晶体管。 用于将脉冲形状信号与由压控振荡器产生的时钟信号进行比较以获得相位差的频率相位比较器包括Bi-CMOS栅极和CMOS栅极。

    Data separator and signal processing circuit with an adjustable window
    10.
    发明授权
    Data separator and signal processing circuit with an adjustable window 失效
    数据分离器和信号处理电路具有可调窗口

    公开(公告)号：US5402274A

    公开(公告)日：1995-03-28

    申请号：US964294

    申请日：1992-10-21

    申请人： Shyoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Satoshi Kawamura ,  Shinichi Kojima ,  Toshiyuki Iseki

    发明人： Shyoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Satoshi Kawamura ,  Shinichi Kojima ,  Toshiyuki Iseki

    IPC分类号： G11B5/012 ,  G11B7/0045 ,  G11B20/10 ,  G11B20/14 ,  G11B27/10 ,  G11B5/09

    CPC分类号： G11B20/10212 ,  G11B20/1403 ,  G11B5/012 ,  G11B7/0045

    摘要： In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.

    摘要翻译： 在用于在盘装置的盘形记录介质上写入/读取数据的信号处理单元中，数据分离器，代码解码器电路，代码编码器和写补偿电路全部构成在单片机 集成电路。 数据分离器将同步时钟与从盘再现的代码数据分离。 码解码器电路从数据分离器产生来自同步时钟的解码数据，并产生同步的代码数据。 代码编码器将从主计算机或磁盘控制器提供的数据编码为代码数据。 写补偿电路相对于写代码数据补偿峰移。 该集成电路由双极CMOS工艺制造，双极晶体管和CMOS晶体管彼此混合。