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公开(公告)号：US20060001473A1
公开(公告)日：2006-01-05
申请号：US11169314
申请日：2005-06-29
申请人： Eiji Yasuda , Kenichi Hidaka , Yasuyuki Masumoto , Tadayoshi Nakatsuka , Atsushi Watanabe , Katsushi Tara
发明人： Eiji Yasuda , Kenichi Hidaka , Yasuyuki Masumoto , Tadayoshi Nakatsuka , Atsushi Watanabe , Katsushi Tara
IPC分类号： H03K17/62
CPC分类号： H03K17/693
摘要： A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.
摘要翻译： 可以使用多个由肖特基结构成的二极管制成的多个控制电压输入端子的电压中选择高电压的二极管逻辑电路一体形成在复合半导体基板上，在该复合半导体基板上，用于切换和用于固定隔离的MESFET级具有 已经形成。 此外，用于切换的MESFET级由控制电压输入端子的数量的电压控制，用于固定隔离的MESFET级由二极管逻辑电路输出的或电压控制。
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公开(公告)号：US06653697B2
公开(公告)日：2003-11-25
申请号：US10104060
申请日：2002-03-25
IPC分类号： H01L31062
CPC分类号： H03K17/693 , H04B1/18 , H04B1/48
摘要： The invention is directed to the provision of a two-input, four-output high frequency switch circuit that can prevent the occurrence of in-band ripples of insertion loss in an ON path. The high frequency switch circuit is constructed from six field effect transistors, and a signal is passed through a selected one of signal paths in the two-input, four-output high frequency signal switch having a total of six signal terminals, wherein four additional field effect transistors, each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of an external circuit, are respectively connected between ground and the signal paths leading to the remaining four signal terminals to which the signal is not passed and which therefore become open ends. When the signal is not passed, the respective four field effect transistors are put in operation, thereby eliminating the effects of standing waves occurring on the respective paths leading to the four signal terminals acting as open ends.
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公开(公告)号：US07337547B2
公开(公告)日：2008-03-04
申请号：US11169314
申请日：2005-06-29
申请人： Eiji Yasuda , Kenichi Hidaka , Yasuyuki Masumoto , Tadayoshi Nakatsuka , Atsushi Watanabe , Katsushi Tara
发明人： Eiji Yasuda , Kenichi Hidaka , Yasuyuki Masumoto , Tadayoshi Nakatsuka , Atsushi Watanabe , Katsushi Tara
CPC分类号： H03K17/693
摘要： A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.
摘要翻译： 可以使用多个由肖特基结构成的二极管制成的多个控制电压输入端子的电压中选择高电压的二极管逻辑电路一体形成在复合半导体基板上，在该复合半导体基板上，用于切换和用于固定隔离的MESFET级具有 已经形成。 此外，用于切换的MESFET级由控制电压输入端子的数量的电压控制，用于固定隔离的MESFET级由二极管逻辑电路输出的或电压控制。
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公开(公告)号：US07106121B2
公开(公告)日：2006-09-12
申请号：US10819976
申请日：2004-04-08
IPC分类号： H03L5/00
CPC分类号： H03K17/687 , H03J2200/29
摘要： One end of each of five resistors is connected to each of the two ends and the respective intermediate points of a cascade of four depression-type FETs, while the other ends of the five resistors are provided with a predetermined voltage. This configuration fixes the source-drain potential of the four FETs. This fixing of the source-drain potential of the FETs permits stable application of a bias voltage for turning ON the FETs between the gate and the source each FET, so as to ensure the ON-OFF switching of the FETs.
摘要翻译： 五个电阻器中的每一个的一端连接到四个凹陷型FET的级联的两端和各中间点中的每一个，而五个电阻器的另一端设置有预定电压。 该配置修复了四个FET的源极 - 漏极电位。 FET的源极 - 漏极电位的这种固定允许稳定地施加用于导通栅极和源极FET之间的FET的偏置电压，以确保FET的导通切换。
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公开(公告)号：US20050270119A1
公开(公告)日：2005-12-08
申请号：US11143632
申请日：2005-06-03
IPC分类号： H01P1/15 , H03K17/693
CPC分类号： H03K17/693
摘要： A semiconductor apparatus is provided which makes it possible to reduce the number of control terminals required for switching through paths of a high frequency signal, simplify the circuit configuration for controlling the terminals, improve an isolation characteristic between on path and off path of a through FET, and obtain a sufficiently high isolation. In this semiconductor apparatus, one specific through FET and each of shunt FETs connected to each of through FETs other than the one specific through FET are simultaneously turned on in response to the same control signal inputted to the same control terminal. Thus, when a high frequency signal leaks from an output terminal to the signal path of the through FET having been turned on, through the signal paths of the through FETs having been turned off, the high frequency signal can be released to GND through the shunt FET having been turned on.
摘要翻译： 提供一种半导体装置，其可以减少切换高频信号的路径所需的控制端子的数量，简化用于控制端子的电路结构，提高通过FET的通路和截止路径之间的隔离特性 ，并获得足够高的隔离度。 在该半导体装置中，响应于输入到同一控制端子的相同的控制信号，一个特定的通过FET和连接到除一个特定通孔之外的每个通孔的分流FET同时导通。 因此，当高频信号从已经导通的通过FET的输出端子泄漏到通过FET的信号路径时，通过截止的通过FET的信号路径，高频信号可以通过分流器被释放到GND FET已经接通。
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6.发明授权公开(公告)号：US08193091B2
公开(公告)日：2012-06-05
申请号：US10173900
申请日：2002-06-19
申请人： Fumihiko Kawai , Toshiyuki Fukuda , Masanori Minamio , Noboru Takeuchi , Shuichi Ogata , Katsushi Tara , Tadayoshi Nakatsuka
发明人： Fumihiko Kawai , Toshiyuki Fukuda , Masanori Minamio , Noboru Takeuchi , Shuichi Ogata , Katsushi Tara , Tadayoshi Nakatsuka
IPC分类号： H01L23/495
CPC分类号： H01L24/49 , H01L21/4842 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06179 , H01L2224/32014 , H01L2224/32245 , H01L2224/45015 , H01L2224/451 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/48471 , H01L2224/49111 , H01L2224/49113 , H01L2224/4912 , H01L2224/4917 , H01L2224/49171 , H01L2224/49175 , H01L2224/49433 , H01L2224/4945 , H01L2224/73265 , H01L2224/85191 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/10161 , H01L2924/10329 , H01L2924/181 , H01L2924/18301 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/48227 , H01L2924/20752 , H01L2924/20753 , H01L2924/00015 , H01L2224/05599 , H01L2224/4554
摘要： The present invention includes a die pad; signal leads, ground connection leads connected to the die pad; a semiconductor chip including electrode pads for grounding; metal thin wires, and an encapsulating resin for encapsulating the die pad and the semiconductor chip and encapsulating the signal leads and the ground connection lead such that lower portions of the signal leads and the ground connection lead are exposed as external terminals. The ground connection lead is connected to the electrode pad for grounding, so that the resin-encapsulated semiconductor device is electrically stabilized. Furthermore, interference between high frequency signals passing through the signal leads can be suppressed by the die pad and the ground connection leads.
摘要翻译： 本发明包括一个管芯焊盘; 信号引线，接地连接引线连接到管芯焊盘; 包括用于接地的电极焊盘的半导体芯片; 金属细线，以及用于封装芯片焊盘和半导体芯片的封装树脂，并封装信号引线和接地连接引线，使得信号引线和接地连接引线的下部被暴露为外部端子。 接地连接引线连接到电极焊盘用于接地，使得树脂封装的半导体器件电稳定。 此外，可以通过管芯焊盘和接地连接引线来抑制通过信号引线的高频信号之间的干扰。
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公开(公告)号：US07199635B2
公开(公告)日：2007-04-03
申请号：US10864352
申请日：2004-06-10
IPC分类号： H03L5/00
CPC分类号： H03K17/102 , H03K17/6871 , H03K17/693 , H03K2217/0036
摘要： The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
摘要翻译： 多个电阻元件的第一端子连接到串联连接的多个FET的中间连接点，并且具有与施加到多个FET的栅极端子的电压相反的相位的电压为 施加到多个电阻元件的第二端子。 利用这种配置，可以防止串联连接的多个FET的中间连接点处的电位降低。 结果，可以提高可以处理的功率。 此外，由于能够防止串联连接的多个FET的中间连接点的电位降低，所以由于多个FET的中间连接点的电位降低，失真特性和隔离特性的劣化 串联连接的场效应晶体管可以获得优异的高频特性。
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公开(公告)号：US07173471B2
公开(公告)日：2007-02-06
申请号：US10864351
申请日：2004-06-10
申请人： Tadayoshi Nakatsuka , Atsushi Suwa , Katsushi Tara
发明人： Tadayoshi Nakatsuka , Atsushi Suwa , Katsushi Tara
IPC分类号： H03L5/00
CPC分类号： H03K17/04123 , H03K17/693
摘要： Four switching circuit sections consisting of four FETs connected in series are provided between a plurality of input/output terminals which output and input a high frequency signal. Gate control voltages are individually applied to gate terminals of four FETs, respectively, so that an on-state and an off-state are achieved. Further drain control voltages are individually applied to drain terminals or source terminals of the FET in each switching circuit section, and a voltage according to an electric power value of the high frequency signal supplied to each of switching circuit sections is supplied as the gate control voltage and the drain control voltage.
摘要翻译： 在串联连接的四个FET组成的四个开关电路部分设置在输出并输入高频信号的多个输入/输出端子之间。 栅极控制电压分别分别施加到四个FET的栅极端子，从而实现导通状态和截止状态。 在各开关电路部分中分别对漏极端子或FET的源极施加进一步的漏极控制电压，并且提供根据提供给每个开关电路部分的高频信号的电功率值的电压作为栅极控制电压 和漏极控制电压。
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公开(公告)号：US07636004B2
公开(公告)日：2009-12-22
申请号：US11672415
申请日：2007-02-07
IPC分类号： H03L5/00
CPC分类号： H03K17/102 , H03K17/6871 , H03K17/693 , H03K2217/0036
摘要： The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
摘要翻译： 多个电阻元件的第一端子连接到串联连接的多个FET的中间连接点，并且具有与施加到多个FET的栅极端子的电压相反的相位的电压为 施加到多个电阻元件的第二端子。 利用这种配置，可以防止串联连接的多个FET的中间连接点处的电位降低。 结果，可以提高可以处理的功率。 此外，由于能够防止串联连接的多个FET的中间连接点的电位降低，所以由于多个FET的中间连接点的电位降低，失真特性和隔离特性的劣化 串联连接的场效应晶体管可以获得优异的高频特性。
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公开(公告)号：US20060181328A1
公开(公告)日：2006-08-17
申请号：US11402849
申请日：2006-04-13
IPC分类号： H03K17/693
CPC分类号： H03K17/102 , H03K17/6871 , H03K17/693 , H03K2217/0036
摘要： The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
摘要翻译： 多个电阻元件的第一端子连接到串联连接的多个FET的中间连接点，并且具有与施加到多个FET的栅极端子的电压相反的相位的电压为 施加到多个电阻元件的第二端子。 利用这种配置，可以防止串联连接的多个FET的中间连接点处的电位降低。 结果，可以提高可以处理的功率。 此外，由于能够防止串联连接的多个FET的中间连接点的电位降低，所以由于多个FET的中间连接点的电位降低，失真特性和隔离特性的劣化 串联连接的场效应晶体管可以获得优异的高频特性。
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