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    High-frequency switch circuit and mobile telecommunications terminal device using the same
    1.
    发明授权
    High-frequency switch circuit and mobile telecommunications terminal device using the same 失效
    高频开关电路和移动电信终端设备使用相同

    公开(公告)号：US07020453B2

    公开(公告)日：2006-03-28

    申请号：US10489816

    申请日：2003-05-21

    申请人： Kenichi Hidaka ,  Tadayoshi Nakatsuka ,  Atsushi Suwa

    发明人： Kenichi Hidaka ,  Tadayoshi Nakatsuka ,  Atsushi Suwa

    IPC分类号： H04B1/28

    CPC分类号： H04W52/029 ,  H04B1/1615 ,  H04B1/44 ,  H04B1/48 ,  H04W52/0274 ,  Y02D70/1222 ,  Y02D70/40

    摘要： An object is to provide an antenna switch semiconductor integrated circuit which reduces a consumption current. To this end, of two control input signals which are fed to a logic circuit which controls turning on and off of a plurality of switching FETs, a control input signal for switching between a sending mode and a receiving mode is fed to an oscillation circuit, thereby making the oscillation circuit operate only during the sending mode under which the logic circuit needs a high voltage. A voltage raising circuit accordingly operates, whereby a raised voltage is supplied to the logic circuit. During the receiving mode, the oscillation circuit stops, and the voltage raising circuit stops. With a switch turned on using the logic circuit, a power source voltage is supplied directly to the logic circuit when the voltage raising circuit is not in operation. This shortens the operation time of the voltage raising circuit and reduces the consumption current.

    摘要翻译： 目的在于提供减少消耗电流的天线开关半导体集成电路。 为此，由馈送到控制多个开关FET的导通和截止的逻辑电路的两个控制输入信号，将用于在发送模式和接收模式之间切换的控制输入信号馈送到振荡电路， 从而使振荡电路仅在逻辑电路需要高电压的发送模式下工作。 升压电路相应地工作，由此向逻辑电路提供升高的电压。 在接收模式下，振荡电路停止，升压电路停止。 当使用逻辑电路接通开关时，当升压电路不工作时，将电源电压直接提供给逻辑电路。 这缩短了升压电路的工作时间，降低了消耗电流。

    High frequency switching circuit device
    2.
    发明申请
    High frequency switching circuit device 有权
    高频开关电路装置

    公开(公告)号：US20060001473A1

    公开(公告)日：2006-01-05

    申请号：US11169314

    申请日：2005-06-29

    申请人： Eiji Yasuda ,  Kenichi Hidaka ,  Yasuyuki Masumoto ,  Tadayoshi Nakatsuka ,  Atsushi Watanabe ,  Katsushi Tara

    发明人： Eiji Yasuda ,  Kenichi Hidaka ,  Yasuyuki Masumoto ,  Tadayoshi Nakatsuka ,  Atsushi Watanabe ,  Katsushi Tara

    IPC分类号： H03K17/62

    CPC分类号： H03K17/693

    摘要： A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

    摘要翻译： 可以使用多个由肖特基结构成的二极管制成的多个控制电压输入端子的电压中选择高电压的二极管逻辑电路一体形成在复合半导体基板上，在该复合半导体基板上，用于切换和用于固定隔离的MESFET级具有 已经形成。 此外，用于切换的MESFET级由控制电压输入端子的数量的电压控制，用于固定隔离的MESFET级由二极管逻辑电路输出的或电压控制。

    Charge pump type booster circuit and antenna switch
    3.
    发明申请
    Charge pump type booster circuit and antenna switch 审中-公开
    电荷泵型升压电路和天线开关

    公开(公告)号：US20060261880A1

    公开(公告)日：2006-11-23

    申请号：US11434055

    申请日：2006-05-16

    申请人： Kenichi Hidaka ,  Tadayoshi Nakatsuka

    发明人： Kenichi Hidaka ,  Tadayoshi Nakatsuka

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07

    摘要： An output voltage Vout from a boost processing section 20 is divided by resistances 41 and 42, and a resultant divided output voltage Va is input to one of two input terminals of a comparator 45. A reference voltage Vb obtained by dividing a voltage Vcc by resistances 43 and 44 is input to the other input terminal of the comparator 45. The comparator 45 compares the divided output voltage Va with the reference voltage Vb, and when the divided output voltage Va is lower, outputs a HIGH voltage, and when the divided output voltage Va is higher, outputs a LOW voltage. Thereby, an signal oscillating section 10 performs oscillation at a radio frequency (an N-type CMOS FET 18 is in the OFF state) when the output voltage Vout does not exceed a threshold value determined by the reference voltage Vb, and performs oscillation at a low frequency (the N-type CMOS FET 18 is in the ON state) when the output voltage Vout exceeds the threshold value.

    摘要翻译： 来自升压处理部分20的输出电压Vout被电阻41和42分压，并且所得到的分压输出电压Va被输入到比较器45的两个输入端之一。通过将电压Vcc除以电阻获得的参考电压Vb 43和44被输入到比较器45的另一个输入端。比较器45将分压后的输出电压Va与参考电压Vb进行比较，当分压后的输出电压Va较低时，输出高电压，分压输出 电压Va较高，输出低电压。 因此，当输出电压Vout不超过由参考电压Vb确定的阈值时，信号振荡部10在射频（N型CMOS FET 18处于截止状态）下进行振荡，并且在 当输出电压Vout超过阈值时，低频（N型CMOS FET 18处于导通状态）。

    High frequency switch circuit and communications terminal using the same
    4.
    发明授权
    High frequency switch circuit and communications terminal using the same 失效

    公开(公告)号：US06653697B2

    公开(公告)日：2003-11-25

    申请号：US10104060

    申请日：2002-03-25

    申请人： Kenichi Hidaka ,  Tadayoshi Nakatsuka ,  Katsushi Tara

    发明人： Kenichi Hidaka ,  Tadayoshi Nakatsuka ,  Katsushi Tara

    IPC分类号： H01L31062

    CPC分类号： H03K17/693 ,  H04B1/18 ,  H04B1/48

    摘要： The invention is directed to the provision of a two-input, four-output high frequency switch circuit that can prevent the occurrence of in-band ripples of insertion loss in an ON path. The high frequency switch circuit is constructed from six field effect transistors, and a signal is passed through a selected one of signal paths in the two-input, four-output high frequency signal switch having a total of six signal terminals, wherein four additional field effect transistors, each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of an external circuit, are respectively connected between ground and the signal paths leading to the remaining four signal terminals to which the signal is not passed and which therefore become open ends. When the signal is not passed, the respective four field effect transistors are put in operation, thereby eliminating the effects of standing waves occurring on the respective paths leading to the four signal terminals acting as open ends.

    High frequency switching circuit device
    5.
    发明授权
    High frequency switching circuit device 有权
    高频开关电路装置

    公开(公告)号：US07337547B2

    公开(公告)日：2008-03-04

    申请号：US11169314

    申请日：2005-06-29

    申请人： Eiji Yasuda ,  Kenichi Hidaka ,  Yasuyuki Masumoto ,  Tadayoshi Nakatsuka ,  Atsushi Watanabe ,  Katsushi Tara

    发明人： Eiji Yasuda ,  Kenichi Hidaka ,  Yasuyuki Masumoto ,  Tadayoshi Nakatsuka ,  Atsushi Watanabe ,  Katsushi Tara

    IPC分类号： H01P1/10 ,  H01P5/12

    CPC分类号： H03K17/693

    摘要： A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

    摘要翻译： 可以使用多个由肖特基结构成的二极管制成的多个控制电压输入端子的电压中选择高电压的二极管逻辑电路一体形成在复合半导体基板上，在该复合半导体基板上，用于切换和用于固定隔离的MESFET级具有 已经形成。 此外，用于切换的MESFET级由控制电压输入端子的数量的电压控制，用于固定隔离的MESFET级由二极管逻辑电路输出的或电压控制。

    High frequency switch circuit
    7.
    发明授权
    High frequency switch circuit 有权
    高频开关电路

    公开(公告)号：US07106121B2

    公开(公告)日：2006-09-12

    申请号：US10819976

    申请日：2004-04-08

    申请人： Kenichi Hidaka ,  Katsushi Tara ,  Tadayoshi Nakatsuka

    发明人： Kenichi Hidaka ,  Katsushi Tara ,  Tadayoshi Nakatsuka

    IPC分类号： H03L5/00

    CPC分类号： H03K17/687 ,  H03J2200/29

    摘要： One end of each of five resistors is connected to each of the two ends and the respective intermediate points of a cascade of four depression-type FETs, while the other ends of the five resistors are provided with a predetermined voltage. This configuration fixes the source-drain potential of the four FETs. This fixing of the source-drain potential of the FETs permits stable application of a bias voltage for turning ON the FETs between the gate and the source each FET, so as to ensure the ON-OFF switching of the FETs.

    摘要翻译： 五个电阻器中的每一个的一端连接到四个凹陷型FET的级联的两端和各中间点中的每一个，而五个电阻器的另一端设置有预定电压。 该配置修复了四个FET的源极 - 漏极电位。 FET的源极 - 漏极电位的这种固定允许稳定地施加用于导通栅极和源极FET之间的FET的偏置电压，以确保FET的导通切换。

    Semiconductor memory device and antifuse programming method
    9.
    发明授权
    Semiconductor memory device and antifuse programming method 有权
    半导体存储器件和反熔丝编程方法

    公开(公告)号：US08982648B2

    公开(公告)日：2015-03-17

    申请号：US13193186

    申请日：2011-07-28

    申请人： Takuji Onuma ,  Kenichi Hidaka ,  Hiromichi Takaoka ,  Yoshitaka Kubota ,  Hiroshi Tsuda

    发明人： Takuji Onuma ,  Kenichi Hidaka ,  Hiromichi Takaoka ,  Yoshitaka Kubota ,  Hiroshi Tsuda

    IPC分类号： G11C7/00 ,  G11C17/18

    CPC分类号： G11C17/18

    摘要： An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.

    摘要翻译： 由NMOS晶体管或NMOS电容器构成的反熔丝包括耦合到栅电极的第一端子，耦合到扩散层的第二端子和介于栅极电极和扩散层之间的栅极绝缘膜。 编程电路包括具有第一电流驱动能力并执行第一编程操作的第一编程电路和具有大于第一电流驱动能力的第二电流驱动能力的第二编程电路，并且执行第二编程操作以跟随第一编程操作 。 在第一编程操作中，第一编程电路通过在第一端子和第二端子之间施加第一编程电压来分解栅极绝缘膜。 在第二编程操作中，第二编程电路在第一端子和第二端子之间施加低于第一编程电压的第二编程电压。

    Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method
    10.
    发明授权
    Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method 有权
    具有存储单元的半导体器件，写入或从存储器单元读取的方法以及半导体器件制造方法

    公开(公告)号：US08675385B2

    公开(公告)日：2014-03-18

    申请号：US13067773

    申请日：2011-06-24

    申请人： Hiromichi Takaoka ,  Kenichi Hidaka ,  Hiroshi Tsuda ,  Kiyokazu Ishige ,  Yoshitaka Kubota ,  Takuji Onuma

    发明人： Hiromichi Takaoka ,  Kenichi Hidaka ,  Hiroshi Tsuda ,  Kiyokazu Ishige ,  Yoshitaka Kubota ,  Takuji Onuma

    IPC分类号： G11C17/08

    CPC分类号： H01L27/101 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.

    摘要翻译： 第一半导体器件形成在衬底上并且包括第一绝缘膜，第一电极和第一扩散层。 第二半导体器件形成在衬底上并且包括第二绝缘膜，第二电极和第二扩散层。 第二电极耦合到第一电极。 控制晶体管允许源极和漏极中的一个耦合到第一电极和第二电极，允许源极和漏极中的另一个耦合到位线，并且允许栅电极耦合到 一个字线。 第一电位控制线耦合到第一扩散层并控制第一扩散层的电位。 第二电位控制线耦合到第二扩散层并控制第二扩散层的电位。