摘要:
A method and system for process model translation is disclosed herein. The method includes generating a common process model based upon a first process model capable of being utilized by a first simulation program. A second process model is then generated based upon the common process model, the second process model being capable of being utilized by a second simulation program.
摘要:
A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.
摘要:
The present invention relates to an improved process for the preparation of choline salt of fenofibric acid corresponding to formula (I). The present invention also provides crystalline polymorphic form of choline salt of fenofibric acid corresponding to formula (I) designated as form A.
摘要:
The present invention relates to an improved process for the preparation of tritylated candesartan acid of formula (I) comprising a step of, reacting candesartan acid of formula (II) with trityl chloride in the presence of a base in a ketonic solvent.
摘要:
A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets. The interconnection further includes a Virtual Channel Memory (VCM) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for connecting the VCR to the compression/decompression circuits, a Parallel Cell Interface (PCI) for connecting the VCM to an ATM network, a Pacing Rate Unit (PCU) for automatically reducing the maximum transmission rate in response to a sensed congestion condition in the network, and a Reduced Instruction Set Computer (RISC) microprocessor for controlling the DMA controller and transfers between the memory, a host and the ATM network, for performing segmentation and reassembly of Conversion Sublayer Payload Data Units (CD-PDUs), and for performing conversion between the ATM Protocol and the MPEG protocol. The compression/decompression and decoder/encoder circuits may utilize MPEG to compress digitized images and motion video into compact data streams that can be moved across networks with bandwidths too narrow to accommodate the uncompressed data. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which can be downloaded at initialization.
摘要:
A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functionality of the cache memory arrays. External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.
摘要:
The power of a signal transmitted from a mobile terminal of a half-duplex TDMA communication system to a base station is controlled by collecting data relating to bit errors in the transmitted signal received on an inbound channel, generating a time-varying statistic of the data. If the time varying statistic indicates that the power should be adjusted, a power control command is embedded in one or more time slots of an outbound channel to the mobile terminal to change the power of the signal. The data may be the bit error rate (BER) reported by a forward error correction decoder and/or returned signal strength information (RSSI). The time varying statistic may be the moving average and standard deviation of the data.
摘要:
A single chip network adapter apparatus has each component disposed on a single semiconductor chip. The network adapter includes a host interface circuit which is adapted for connection directly to a host system bus. The host interface circuit sends information to and receives information form the host system bus, and has random access memory coupled thereto. A processor is coupled to the random access memory and formats information received from the host system bus to a network protocol format. The processor also converts information received in a network protocol format to a form suitable for the host system bus. A network interface circuit is coupled to the random access memory and is adapted for connection directly to a network. The network interface circuit sends information formatted by the processor to the network and receives information to be converted by the processor from the network.
摘要:
A digital network system accommodates a plurality of network protocols. The digital network system includes a backbone bus for communicating digital information. A first switching interface unit is coupled to the backbone bus and has at least one port connected to a first network. A second switching interface unit is also coupled to the backbone bus and has at least one port connected to a second network. The first and second interface units transferring digital information in first and second network protocols, respectively. First and second memories are coupled to the backbone bus and to the first and second switching interface units, respectively, and store digital information to be transferred between the switching interface units via the backbone bus. The first switching interface unit and the first memory are formed on a single substrate, and the second switching interface unit and the second memory are formed on a single substrate. A controller is coupled to the backbone bus and controls the transfer of digital information from the first switching interface unit to the second switching interface unit.
摘要:
A single chip network interface apparatus includes a host interface circuit for communication with a host system bus, a network interface circuit for interfacing with a network bus, a dual port RAM coupled to the host interface circuit and also coupled to the network interface circuit, and a processor coupled to the dual port ram for converting packets of information between network protocol format and a format suitable for the host system bus.