Method of manufacturing a semiconductor device
    1.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号:US4352724A

    公开(公告)日:1982-10-05

    申请号:US208391

    申请日:1980-11-19

    摘要: A method of manufacturing a semiconductor device having a multi-layer structure comprises the steps of patterning in accordance with a predetermined pattern a thin film of photoresist formed on a film to be etched which has been formed on a semiconductor substrate, etching the film to be etched partly by an isotropic etching using said patterned film as a mask, completing the etching by an anisotropic etching in the direction of its depth, resulting in tapered or inclined sides on the etched film. The isotropic and anisotropic etchings may be carried out in the same apparatus by changing the reactive gases used in these etchings and/or the conditions of each etching, such as the amount of gas, the gas pressure and the applied radio frequency power.

    摘要翻译: 一种制造具有多层结构的半导体器件的方法包括以下步骤:根据预定图案将形成在待蚀刻的膜上的光致抗蚀剂薄膜形成在半导体衬底上,将该膜蚀刻成 通过使用所述图案化膜作为掩模的各向同性蚀刻部分地蚀刻,通过在其深度方向上的各向异性蚀刻完成蚀刻,导致蚀刻膜上的锥形或倾斜侧。 各向同性和各向异性蚀刻可以通过改变在这些蚀刻中使用的反应气体和/或每个蚀刻的条件,例如气体量,气体压力和施加的射频功率,在相同的装置中进行。

    Process for fabricating a semiconductor device
    2.
    发明授权
    Process for fabricating a semiconductor device 失效
    制造半导体器件的工艺

    公开(公告)号:US4654113A

    公开(公告)日:1987-03-31

    申请号:US698901

    申请日:1985-02-06

    摘要: A method of forming an insulating layer having a planar surf on a lower wiring layer having given patterns steps at the shoulders of the patterns. On a lower wiring layer, a lower insulating layer is formed and a heat resistive material is coated over the lower insulative layer to form a substantially a planar top surface and to fill cavities appearing in the surface of the lower insulating layer with the material. Then, etching is carried out to preserve the profile of the surface of the coating layer and to remove the coating layer at portions where through-holes are to be formed. Any cavities in the surface of the lower insulating layer remain filled with the material after etching. An upper insulating layer is deposited on the exposed lower insulating layer and the remaining part of the coating layer. Through-holes and an upper wiring layer of given patterns are formed so that the upper wiring layer has no contact with the remaining part of the coating layer and so that the remaining part of the coating layer is never externally exposed.

    摘要翻译: 在图案的肩部具有给定图案步骤的下布线层上形成具有平面冲浪的绝缘层的方法。 在下布线层上,形成下绝缘层,并且在下绝缘层上涂覆耐热材料以形成基本上平坦的顶表面,并用该材料填充出现在下绝缘层表面的空腔。 然后,进行蚀刻以保持涂层表面的轮廓,并在要形成通孔的部分去除涂层。 蚀刻后,下绝缘层的表面中的任何空腔都保持填充材料。 在暴露的下绝缘层和涂层的其余部分上沉积上绝缘层。 形成具有给定图案的通孔和上布线层,使得上布线层与涂层的剩余部分没有接触,从而使外涂层的剩余部分不会外露。

    Process for fabricating a wiring layer of aluminum or aluminum alloy on
semiconductor devices
    3.
    发明授权
    Process for fabricating a wiring layer of aluminum or aluminum alloy on semiconductor devices 失效
    在半导体器件上制造铝或铝合金的布线层的工艺

    公开(公告)号:US4547260A

    公开(公告)日:1985-10-15

    申请号:US598741

    申请日:1984-04-10

    CPC分类号: H01L21/02071 H01L21/302

    摘要: In the fabrication of an aluminum or aluminum alloy wiring layer on a semiconductor device by dry etching using a gas containing chlorine species, a plasma exposure step inserted into the dry etching process in order to avoid the problems due to using a chlorine radical etchant. One half thickness of the aluminum layer, which is selectively masked by a resist mask film, on a semiconductor substrate is etched by a reactive ion etching technique using an etchant gas composed of CCl.sub.4 +BCl.sub.3, and then exposed to a plasma of a gas composed of CF.sub.4 +O.sub.2 generated by RF power. After the plasma exposure, the remaining thickness of the aluminum film is etched off under the same conditions as in the preceeding reactive ion etching. As the result, the amount of side etching is reduced to one half that of the case without the plasma exposure step, and corrosion originating from aluminum chlorides, products of the reactive ion etching, is eliminated. And further, the residual polysilicon layer, which is usually formed when Al-Si film is etched by using a gas containing chlorine as a reactive species, is also reduced.

    摘要翻译: 在通过使用含氯气体的干蚀刻在半导体器件上制造铝或铝合金布线层时,将等离子体暴露步骤插入到干蚀刻工艺中,以避免由于使用氯根腐蚀剂而引起的问题。 通过使用由CCl 4 + BCl 3组成的蚀刻剂气体的反应离子蚀刻技术蚀刻在半导体衬底上被抗蚀剂掩模膜选择性地掩蔽的铝层的一半厚度,然后暴露于构成的气体的等离子体 由RF功率产生的CF4 + O2。 在等离子体暴露后,在与之前的反应离子蚀刻相同的条件下,蚀刻掉铝膜的剩余厚度。 结果,侧蚀刻的量减少到没有等离子体曝光步骤的情况的一半,并且消除了源自氯化铝的腐蚀反应离子蚀刻产物的腐蚀。 此外,通过使用含氯气体作为反应性物质蚀刻Al-Si膜时通常形成的残留多晶硅层也减少。

    Etching method for semiconductor devices
    4.
    发明授权
    Etching method for semiconductor devices 失效
    半导体器件蚀刻方法

    公开(公告)号:US4545851A

    公开(公告)日:1985-10-08

    申请号:US605908

    申请日:1984-05-01

    申请人: Tadakazu Takada

    发明人: Tadakazu Takada

    摘要: An etching method for fabricating a contact hole in an insulating layer between multi-layered wiring layers of a semiconductor device. Etching is performed by chemical dry etching, in which the plasma of the etchant gas is formed in a separate chamber and fed to the etching chamber. The substrate is covered with a photo resist mask which includes a pattern hole and is heated, from the side opposite the mask, up to a softening temperature of the photo resist. The edge of the photo resist mask surrounding the pattern hole gradually rolls up as side etching proceeds under the edge of the photo resist mask with the result that the side walls of the contact hole are tapered. Consequently, the subsequently formed wiring layer formed thereon has good step coverage over the side walls of the contact hole, so that discontinuities and breakage of the wiring layer is prevented and the reliability and yield of the manufacturing process are improved.

    摘要翻译: 一种用于在半导体器件的多层布线层之间的绝缘层中制造接触孔的蚀刻方法。 蚀刻通过化学干蚀刻进行,其中蚀刻剂气体的等离子体形成在单独的室中并被供给到蚀刻室。 用包括图形孔的光致抗蚀剂掩模覆盖基板,并且从与掩模相对的一侧被加热到光致抗蚀剂的软化温度。 围绕图案孔的光刻胶掩模的边缘随着在光致抗蚀剂掩模的边缘进行侧蚀刻而逐渐卷起,结果接触孔的侧壁是锥形的。 因此,形成在其上的后续形成的布线层在接触孔的侧壁上具有良好的阶梯覆盖,从而防止了布线层的不连续性和断裂,并且提高了制造工艺的可靠性和良率。