公开(公告)号：US08358509B2

公开(公告)日：2013-01-22

申请号：US12362649

申请日：2009-01-30

申请人： Kevin J. Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Lloyd A. Walls

发明人： Kevin J. Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Lloyd A. Walls

IPC分类号： H05K3/00

CPC分类号： H04B1/04 ,  H03M3/024

摘要： An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit and the plurality of electronic components, wherein the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation to provide a slope directly proportional to a data value.

摘要翻译： 信息处理系统装置包括多个电子部件; 电路，包括用于连接所述多个电子部件中的两个或更多个的至少一个迹线，以及经由至少一个电信号在所述多个电子部件之间传输数据; 以及包括用作电路和多个电子部件的基底的绝缘材料的基板，其中在所述多个电子部件之间传输的所述至少一个电信号利用斜率操作来传输，以提供与 数据值。

公开(公告)号：US08743558B2

公开(公告)日：2014-06-03

申请号：US13614119

申请日：2012-09-13

申请人： Kevin J. Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Lloyd A. Walls

发明人： Kevin J. Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Lloyd A. Walls

IPC分类号： H05K7/00

CPC分类号： H04B1/04 ,  H03M3/024

摘要： An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages.

摘要翻译： 信息处理系统装置包括多个电子部件; 电路，包括用于连接所述多个电子部件中的两个或更多个的至少一个迹线，以及经由至少一个电信号在所述多个电子部件之间传输数据; 以及包括用作电路的基底的绝缘材料的基板，其中在所述多个电子部件之间传输的所述至少一个电信号中的每一个通过操纵所述至少一个电信号中的每个电信号而利用斜率操作传输，以提供 基本上与n个离散整数数据值的离散整数数据值成比例的斜率，n是大于或等于3的正整数，所述离散整数数据值使用n个不同斜率之一表示，所述斜率使用n的特定参考电压 预定参考电压。

公开(公告)号：US20130010445A1

公开(公告)日：2013-01-10

申请号：US13614119

申请日：2012-09-13

申请人： Kevin J. Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Lloyd A. Walls

发明人： Kevin J. Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Lloyd A. Walls

IPC分类号： H05K7/00

CPC分类号： H04B1/04 ,  H03M3/024

摘要： An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages.

摘要翻译： 信息处理系统装置包括多个电子部件; 电路，包括用于连接所述多个电子部件中的两个或更多个的至少一个迹线，以及经由至少一个电信号在所述多个电子部件之间传输数据; 以及包括用作电路的基底的绝缘材料的基板，其中在所述多个电子部件之间传输的所述至少一个电信号中的每一个通过操纵所述至少一个电信号中的每个电信号而利用斜率操作传输，以提供 基本上与n个离散整数数据值的离散整数数据值成比例的斜率，n是大于或等于3的正整数，所述离散整数数据值使用n个不同斜率之一表示，所述斜率使用n的特定参考电压 预定参考电压。

公开(公告)号：US20100195756A1

公开(公告)日：2010-08-05

申请号：US12362649

申请日：2009-01-30

申请人： Kevin J. Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Lloyd A. Walls

发明人： Kevin J. Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Lloyd A. Walls

IPC分类号： H04L27/00

CPC分类号： H04B1/04 ,  H03M3/024

摘要： An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit and the plurality of electronic components, wherein the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation to provide a slope directly proportional to a data value.

摘要翻译： 信息处理系统装置包括多个电子部件; 电路，包括用于连接所述多个电子部件中的两个或更多个的至少一个迹线，以及经由至少一个电信号在所述多个电子部件之间传输数据; 以及包括用作电路和多个电子部件的基底的绝缘材料的基板，其中在所述多个电子部件之间传输的所述至少一个电信号利用斜率操作来传输，以提供与 数据值。

公开(公告)号：US08425115B2

公开(公告)日：2013-04-23

申请号：US13077139

申请日：2011-03-31

申请人： Aquilur Rahman ,  Lloyd A. Walls

发明人： Aquilur Rahman ,  Lloyd A. Walls

IPC分类号： G01K7/16 ,  H01L23/48

CPC分类号： G01K7/16 ,  G01K1/14

摘要： A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, first linear conductive members are positioned in a first IC layer, in parallel relationship with one another. Second linear conductive members are positioned in a second IC layer in parallel relationship with one another. Conductive elements connect the first linear members into a first conductive path, and the second linear members into a second conductive path. A third conductive element extending between the first and second layers connects the first and second conductive paths into a single conductive path, wherein the path resistance varies with temperature. The path resistance is used to determine temperature.

摘要翻译： 为集成电路（IC）提供了紧凑的电阻式热传感器，其中不同的传感器部件被放置在IC的不同层上。 这允许选择性地减少任何特定IC层上的传感器电阻线所需的横向面积。 在有用的实施例中，第一线性导电构件彼此平行地定位在第一IC层中。 第二线性导电构件彼此平行地定位在第二IC层中。 导电元件将第一线性构件连接到第一导电路径中，并将第二线性构件连接到第二导电路径中。 在第一和第二层之间延伸的第三导电元件将第一和第二导电路径连接成单个导电路径，其中路径电阻随温度而变化。 路径电阻用于确定温度。

公开(公告)号：US20080093726A1

公开(公告)日：2008-04-24

申请号：US11551888

申请日：2006-10-23

申请人： Francesco Preda ,  Lloyd A. Walls

发明人： Francesco Preda ,  Lloyd A. Walls

IPC分类号： H01L23/12

CPC分类号： H01L23/50 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

摘要： A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

摘要翻译： 用于在层压封装中连续地参考多层信号的机构提供了用于从一层到另一层的信号的连续路径，同时使用用于封装的所有区域的理想电压基准并且仍避免电压基准中的不连续性。 参考平面调整引擎分析封装设计，并为封装的所有区域（包括特定芯片裸片下的区域）和不在芯片裸片下的区域识别理想的顶层平面。 参考平面调整引擎然后修改封装设计以重新定位层之间的接地层，源电压平面，信号面和通孔，以保持连续的电压基准，而不管顶层如何。 参考平面调整引擎将所形成的混合电压平面封装设计提供给设计分析引擎。 包装制造系统制造包装。

公开(公告)号：US5541535A

公开(公告)日：1996-07-30

申请号：US357885

申请日：1994-12-16

申请人： Tai A. Cao ,  Satyajit Dutta ,  Thai Q. Nguyen ,  Thanh D. Trinh ,  Lloyd A. Walls

发明人： Tai A. Cao ,  Satyajit Dutta ,  Thai Q. Nguyen ,  Thanh D. Trinh ,  Lloyd A. Walls

IPC分类号： H04L5/14 ,  H03K19/0185

CPC分类号： H04L5/1423

摘要： A CMOS driver/receiver pair is provided which includes a non-inverting buffer in the input path to a differential receiver circuit. The non-inverting buffer allows a plurality of different voltages, and corresponding voltage swings, to be possible. This allows the differential receiver to compare the input voltage received from the transmission line with the output from its associated driver. Therefore, the receiver is capable of determining the voltage level (and the corresponding logic level) input from the transmission at the same time its associated driver is outputting a logic signal to another driver/receiver pair, via the transmission line. A single voltage source is utilized to provide multiple positive voltages to the differential receivers, such that differences in voltage levels which correspond to different logical combinations of "1" and "0" can be determined by the receiver.

摘要翻译： 提供了CMOS驱动器/接收器对，其包括到差分接收器电路的输入路径中的非反相缓冲器。 非反相缓冲器允许多个不同的电压和相应的电压摆幅是可能的。 这允许差分接收器将从传输线接收的输入电压与其相关联的驱动器的输出进行比较。 因此，接收机能够确定从传输输入的电压电平（和相应的逻辑电平），同时其相关联的驱动器通过传输线将逻辑信号输出到另一个驱动器/接收器对。 使用单个电压源来向差分接收器提供多个正电压，使得对应于“1”和“0”的不同逻辑组合的电压电平差可由接收器确定。

公开(公告)号：US5534812A

公开(公告)日：1996-07-09

申请号：US426753

申请日：1995-04-21

申请人： Tai A. Cao ,  Satyajit Dutta ,  Thai Q. Nguyen ,  Thanh D. Trinh ,  Lloyd A. Walls

发明人： Tai A. Cao ,  Satyajit Dutta ,  Thai Q. Nguyen ,  Thanh D. Trinh ,  Lloyd A. Walls

IPC分类号： H03K19/00 ,  H04L25/02 ,  H03L5/00

CPC分类号： H04L25/028 ,  H03K19/0005 ,  H04L25/0278

摘要： The present invention includes an output circuit for a driver on a first chip that will cause an unterminated transmission line to create a predetermined voltage reflection. This reflection will then be added to the output of the driver circuit to obtain a voltage level capable of switching the receiver circuit, located on a second chip. Further, the impedance of the driver can be varied to adjust the voltage level of the signal being transmitted to the receiver, in order to reduce noise margins and cause the receiver to switch more quickly. Additionally, the transmission line impedance can also be modified to create overshoot, thereby allowing chips with dissimilar voltage levels to communicate with one another.

摘要翻译： 本发明包括用于第一芯片上的驱动器的输出电路，其将导致未终止的传输线路产生预定的电压反射。 然后将该反射加到驱动器电路的输出端，以获得能够切换位于第二芯片上的接收器电路的电压电平。 此外，可以改变驱动器的阻抗以调节正在传输到接收器的信号的电压电平，以便降低噪声容限并使接收器更快地切换。 此外，还可以修改传输线路阻抗以产生过冲，从而允许具有不同电压电平的芯片彼此通信。

公开(公告)号：US4862077A

公开(公告)日：1989-08-29

申请号：US311448

申请日：1989-02-13

申请人： Timothy A. Horel ,  Edward S. Hoyt ,  Lloyd A. Walls

发明人： Timothy A. Horel ,  Edward S. Hoyt ,  Lloyd A. Walls

IPC分类号： G01R1/073

CPC分类号： G01R1/07364 ,  G01R1/07342

摘要： A probe card apparatus and method which allows reconfiguration of the probing circuits. A first probe card member has a plurality of incomplete probing circuits which are associated with a plurality of contact holes. An adapter ring member, having a plurality of T-shaped conductive lines terminated in contact holes, is removably mounted in close proximity to the first probe card member. Spring-loaded contact pins provide contact between the members such that the T-shaped conductive lines are used to complete the probing circuit. The T-shaped conductive lines are severable lines, and discrete electronic components can be connected between respective contact holes. As the adapter ring member is of a removably attachable construction, the entire probe card circuitry is reconfigurable by a simple change of the adaptor ring.

摘要翻译： 一种允许重新配置探测电路的探针卡装置和方法。 第一探针卡构件具有与多个接触孔相关联的多个不完全探测电路。 具有端接在接触孔中的多个T形导电线的适配环构件可拆卸地安装在第一探针卡构件附近。 弹簧加载的接触针提供构件之间的接触，使得T形导电线用于完成探测电路。 T形导线是可分离的线，并且分立的电子部件可以连接在相应的接触孔之间。 由于适配器环构件具有可移除地附接结构，所以可以通过适配器环的简单改变来重构整个探针卡电路。

公开(公告)号：US4459609A

公开(公告)日：1984-07-10

申请号：US301563

申请日：1981-09-14

申请人： John A. Fifield ,  Lawrence G. Heller ,  Lloyd A. Walls

发明人： John A. Fifield ,  Lawrence G. Heller ,  Lloyd A. Walls

IPC分类号： G11C11/404 ,  G11C11/56 ,  G11C27/02 ,  H01L29/78 ,  G11C11/24 ,  H01L27/02

CPC分类号： G11C11/404 ,  G11C11/565 ,  G11C27/024 ,  Y10S257/92

摘要： A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.

摘要翻译： 提供了一种密集存储器，其包括使用电荷填充和溢出技术的一个器件随机存取存储器单元，其中存储节点下方的势阱填充有电荷，并且超过预定水平的超量电荷溢出到连接到 通过由字线上的脉冲控制的通道区域的感测线。 信息的一位或两位或更多位可以在任何给定的时刻存储在潜在井中。 取决于施加到存储节点或电极的电压增量的值，给定的模拟电荷包被存储在形成在存储电极下方的势阱中。 通过向字线施加电压来读取信息以打开通道区域，然后以分数，优选为一半的增量降低存储电极上的电压。 通过连接到感测线的感测电路来检测从存储电极下方的电位阱溢出的电荷分组的充电。 为了将信息重写到势阱中，电压的原始增量被施加到存储节点，并且感测线被拉到地，使得扩散区充当势阱的电荷源。