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    Method to achieve increased trench depth, independent of CD as defined by lithography
    1.
    发明授权
    Method to achieve increased trench depth, independent of CD as defined by lithography 失效
    实现增加沟槽深度的方法，与光刻所定义的CD无关

    公开(公告)号：US07144769B2

    公开(公告)日：2006-12-05

    申请号：US10899758

    申请日：2004-07-27

    申请人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

    发明人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/76895

    摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

    摘要翻译： 提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。 该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。 每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。 为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。

    Method to achieve increased trench depth, independent of CD as defined by lithography
    2.
    发明授权
    Method to achieve increased trench depth, independent of CD as defined by lithography 失效
    实现增加沟槽深度的方法，与光刻所定义的CD无关

    公开(公告)号：US06821864B2

    公开(公告)日：2004-11-23

    申请号：US10093789

    申请日：2002-03-07

    申请人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

    发明人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

    IPC分类号： H01L2176

    CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/76895

    摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

    摘要翻译： 提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。 该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。 每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。 为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。

    CONTROL OF DRY CLEAN PROCESS IN WAFER PROCESSING
    4.
    发明申请
    CONTROL OF DRY CLEAN PROCESS IN WAFER PROCESSING 审中-公开
    干法处理干燥过程控制

    公开(公告)号：US20080190446A1

    公开(公告)日：2008-08-14

    申请号：US11674218

    申请日：2007-02-13

    申请人： Rajiv M. Ranade ,  Subhash B. Kulkarni ,  Ole Krogh ,  Sukesh Patel

    发明人： Rajiv M. Ranade ,  Subhash B. Kulkarni ,  Ole Krogh ,  Sukesh Patel

    IPC分类号： B08B6/00

    CPC分类号： H01L21/6833 ,  H01L21/67028 ,  H01L21/67051

    摘要： A “wafer-less” etch chamber cleaning method varies the capacitance applied to radio frequency components of the chuck that is within the etch chamber (varies impedance of the chuck) so as to cause electric field lines within the etch chamber to terminate (bend) away from the chuck. Then the etch chamber can be cleaned using a very aggressive etch chemistry (e.g., NF3) that would otherwise damage the chuck; however, the electric field lines protect the chuck from the etch chemistry. The capacitance is varied according to a pre-established model. Further, the process evaluates the effectiveness of the pre-established model to produce feedback and constantly adjusts the pre-established model to increase the effectiveness of the cleaning process (according to the feedback).

    摘要翻译： “无晶圆”蚀刻室清洁方法改变施加到蚀刻室内的卡盘的射频分量（改变卡盘的阻抗）的电容，以使蚀刻室内的电场线终止（弯曲） 远离卡盘 然后可以使用非常有侵蚀性的蚀刻化学品（例如，NF 3 3）清洁蚀刻室，否则会损坏卡盘; 然而，电场线路保护卡盘免受蚀刻化学物质的影响。 电容根据预先建立的模型而变化。 此外，该过程评估预先建立的模型的有效性以产生反馈并且不断调整预先建立的模型以增加清洁过程的有效性（根据反馈）。

    Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture
    6.
    发明授权
    Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture 失效
    绝缘体上硅芯片具有可靠性和制造工艺的隔离屏障

    公开(公告)号：US6133610A

    公开(公告)日：2000-10-17

    申请号：US9445

    申请日：1998-01-20

    申请人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

    发明人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

    IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

    CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636 ,  H01L29/78648 ,  H01L21/76283

    摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

    摘要翻译： 具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。 栅极沉积在硅层上方。 第一金属触点沉积在栅极上方以形成与栅极的电接触。 沉积第二和第三金属触点以形成与硅层的电接触。 隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。 隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。 还公开了制造SOI芯片的方法。

    Semiconductor manufacturing process for low dislocation defects
    7.
    发明授权
    Semiconductor manufacturing process for low dislocation defects 失效
    低位错缺陷的半导体制造工艺

    公开(公告)号：US5562770A

    公开(公告)日：1996-10-08

    申请号：US343152

    申请日：1994-11-22

    申请人： Bomy A. Chen ,  Terence B. Hook ,  Subhash B. Kulkarni

    发明人： Bomy A. Chen ,  Terence B. Hook ,  Subhash B. Kulkarni

    IPC分类号： H01L21/205 ,  C30B25/18 ,  H01L21/8249 ,  H01L27/06

    CPC分类号： C30B25/18 ,  Y10S438/938

    摘要： The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.

    摘要翻译： 本发明提供了一种全局应力修饰的方法，其导致半导体衬底上的外延生长的半导体器件层中的位错数目，其中器件层和衬底具有晶格失配。 本发明教导了一种通过从衬底的背面移除薄膜层或者添加薄膜层而向衬底赋予凸曲率的方法，以便在器件层中实现位错密度的降低。

    Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability
    9.
    发明授权
    Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability 有权
    制造具有隔离屏障的绝缘体上硅芯片的可靠性的工艺

    公开(公告)号：US06281095B1

    公开(公告)日：2001-08-28

    申请号：US09148918

    申请日：1998-09-04

    申请人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

    发明人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

    IPC分类号： H01L21301

    CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636 ,  H01L29/78648

    摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

    摘要翻译： 具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。 栅极沉积在硅层上方。 第一金属触点沉积在栅极上方以形成与栅极的电接触。 沉积第二和第三金属触点以形成与硅层的电接触。 隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。 隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。 还公开了制造SOI芯片的方法。