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1.发明授权公开(公告)号：US06809005B2
公开(公告)日：2004-10-26
申请号：US10386880
申请日：2003-03-12
IPC分类号： H01L2176
CPC分类号： H01L27/1087 , H01L21/0237 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/763 , H01L29/66181
摘要： The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.
摘要翻译： 本发明提供了在其中制造基本上无空隙填料的沟槽结构的方法。 填料可以从诸如沿沟槽的侧壁形成的多晶硅的衬垫材料生长。 先前形成的空隙可以通过暴露空隙和生长外延硅来治愈。
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2.发明授权Method to achieve increased trench depth, independent of CD as defined by lithography 失效实现增加沟槽深度的方法，与光刻所定义的CD无关公开(公告)号：US06821864B2
公开(公告)日：2004-11-23
申请号：US10093789
申请日：2002-03-07
IPC分类号： H01L2176
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/76224 , H01L21/76895
摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.
摘要翻译： 提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。 该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。 每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。 为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。
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3.发明授权Method to achieve increased trench depth, independent of CD as defined by lithography 失效实现增加沟槽深度的方法，与光刻所定义的CD无关公开(公告)号：US07144769B2
公开(公告)日：2006-12-05
申请号：US10899758
申请日：2004-07-27
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/76224 , H01L21/76895
摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.
摘要翻译： 提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。 该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。 每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。 为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。
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公开(公告)号：US06544838B2
公开(公告)日：2003-04-08
申请号：US09805071
申请日：2001-03-13
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/3065 , H01L21/3081
摘要： A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.
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公开(公告)号：US06489249B1
公开(公告)日：2002-12-03
申请号：US09597441
申请日：2000-06-20
申请人： Gangadhara S. Mathad , Rajiv Ranade
发明人： Gangadhara S. Mathad , Rajiv Ranade
IPC分类号： H01L2100
CPC分类号： H01J37/32623 , H01J37/32642 , H01L21/3065 , Y10S156/915
摘要： In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate “black silicon” comprising: a) providing a plasma etch reactor comprising walls defining an etch chamber; b) providing a plasma source chamber remote from and in communication with the etch chamber to provide a plasma to the etch chamber, and a wafer chuck or pedestal disposed in the etch chamber to seat a wafer; c) providing a dielectric wall in proximity to and around a periphery of the wafer; d) providing a modification to a lower Rf electrode by interposing conductor means into an extension of Vdc flat sheath boundary relationship to the dielectric wall means and the wafer or in substitution for the dielectric wall; e) forming a plasma within the plasma source chamber and providing the plasma to the etch chamber; and f) supplying Rf energy to the wafer chuck to assist etching of the wafer by forming electric fields between the upper surface of the wafer and the walls of the etch chamber, to provide extension of a Vdc flat sheath boundary beyond and into a defocusing relationship to the wafer edge to reduce mask erosion and eliminate occurrence of “black silicon” formation.
摘要翻译： 在蚀刻等离子体蚀刻反应器中的晶片的方法中，改进导电蚀刻以减少或消除“黑硅”，包括：a）提供包含限定蚀刻室的壁的等离子体蚀刻反应器; b）提供等离子体源室远离 提供等离子体到蚀刻室，以及设置在蚀刻室中以安置晶片的晶片卡盘或基座; c）在晶片的周边附近和周围提供电介质壁; d）通过将导体装置插入到电介质壁装置和晶片的Vdc平面鞘边界关系的延伸部中或代替电介质壁来提供对下部Rf电极的修改; e）在等离子体源室内形成等离子体;以及 将等离子体提供给蚀刻室; 以及f）通过在晶片的上表面和蚀刻室的壁之间形成电场来提供晶片卡盘的Rf能量以辅助晶片的蚀刻，以提供超过Vdc平坦护套边界超过和散焦关系的Vdc 晶圆边缘减少掩模侵蚀，消除“黑硅”形成的发生。
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公开(公告)号：US06687014B2
公开(公告)日：2004-02-03
申请号：US10050737
申请日：2002-01-16
IPC分类号： G01B902
CPC分类号： G01B11/0683 , G01B11/0675
摘要： A method of measuring the rate of etching of trenches on a substrate using interferometry is provided. The method comprises transmitting onto the substrate incident electromagnetic radiation having a wavelength above the wavelength at which the trenches act as waveguides for the radiation; collecting reflected electromagnetic radiation from the substrate; detecting a repetitive pattern of maximum intensities and minimum intensities of the reflected electromagnetic radiation during the etching; and determining the rate of etching based upon the wavelength of the incident electromagnetic radiation and the time period of the pattern.
摘要翻译： 提供了使用干涉测量法测量衬底上的沟槽的蚀刻速率的方法。 所述方法包括将具有波长高于波导的波长的入射电磁辐射传输到所述基底上，所述波长在所述波长处作为所述辐射的波导; 收集来自基板的反射电磁辐射; 在蚀刻期间检测反射电磁辐射的最大强度和最小强度的重复图案; 以及基于入射的电磁辐射的波长和图案的时间周期来确定蚀刻速率。
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公开(公告)号：US4671849A
公开(公告)日：1987-06-09
申请号：US730976
申请日：1985-05-06
申请人： Lee Chen , Gangadhara S. Mathad
发明人： Lee Chen , Gangadhara S. Mathad
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/308 , C23F1/02
CPC分类号： H01L21/31116
摘要： A method for precisely controlling the profile of an opening etched in a layer of material, for example, an insulating layer. In one embodiment, wherein a silicon dioxide layer is reactive ion etched through a photoresist mask, the concentration of a reactive species in an etchant gas is changed during the etching process to change the slope of the opening, the upper sidewall portion of the opening having a shallow slope and the lower sidewall portion of the opening having a steep slope. The final slope of the opening formed by this method is independent of the initial slopes of the images developed in the photoresist mask.
摘要翻译： 一种用于精确地控制蚀刻在材料层（例如绝缘层）中的开口的轮廓的方法。 在一个实施方案中，其中二氧化硅层是通过光致抗蚀剂掩模进行反应离子蚀刻，蚀刻剂气体中的反应性物质的浓度在蚀刻过程中改变以改变开口的斜率，开口的上侧壁部分具有 开口的浅斜面和下侧壁部分具有陡峭的斜坡。 通过该方法形成的开口的最终斜率与在光致抗蚀剂掩模中显影的图像的初始斜率无关。
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公开(公告)号：US4534816A
公开(公告)日：1985-08-13
申请号：US623670
申请日：1984-06-22
IPC分类号： H01L21/302 , H01J37/32 , H01L21/00 , H01L21/3065 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L21/67069 , H01J37/3244 , H01J37/32532 , H01J37/32623
摘要： A high pressure, high etch rate single wafer plasma reactor having a fluid cooled upper electrode including a plurality of small diameter holes or passages therethrough to provide uniform reactive gas distribution over the surface of a wafer to be etched. A fluid cooled lower electrode is spaced from the upper electrode to provide an aspect ratio (wafer diameter: spacing) greater than about 25, and includes an insulating ring at its upper surface. The insulating ring protrudes above the exposed surface of the lower electrode to control the electrode spacing and to provide a plasma confinement region whereby substantially all of the RF power is dissipated by the wafer. A plurality of spaced apart, radially extending passages through the insulating ring provide a means of uniformly exhausting the reactive gas from the plasma confinement region. Affixed to the upper electrode is a first housing which supplies reactive gas and cooling fluid, and a baffle affixed to the first housing intermediate the upper electrode and a gas inlet forms a plenum above the upper electrode and ensures uniform reactive gas distribution thereover. The first housing and upper electrode are contained within a second housing with an insulating housing therebetween. The upper and lower electrodes are electrically isolated from each other and from ground, so that either or both electrodes may be powered.
摘要翻译： 高压，高蚀刻速率的单晶片等离子体反应器，其具有流体冷却的上部电极，其包括多个小直径孔或穿过其中的通道，以在要蚀刻的晶片的表面上提供均匀的反应气体分布。 流体冷却的下电极与上电极隔开以提供大于约25的纵横比（晶片直径：间距），并且在其上表面包括绝缘环。 绝缘环突出在下电极的暴露表面之上，以控制电极间距并提供等离子体约束区域，从而基本上所有的RF功率都被晶片消散。 通过绝缘环的多个间隔开的径向延伸通道提供均匀排出来自等离子体限制区域的反应气体的装置。 与上电极相连的是提供反应性气体和冷却流体的第一壳体，以及固定在上电极之间的第一壳体的挡板和气体入口在上电极上形成集气室，并确保其上的均匀的反应气体分布。 第一壳体和上电极容纳在第二壳体中，其间具有绝缘壳体。 上电极和下电极彼此电隔离并且与地电隔离，使得电极或电极都可以被供电。
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公开(公告)号：US4490211A
公开(公告)日：1984-12-25
申请号：US573452
申请日：1984-01-24
申请人： Lee Chen , John R. Lankard , Gangadhara S. Mathad
发明人： Lee Chen , John R. Lankard , Gangadhara S. Mathad
IPC分类号： C23F4/00 , C23F4/02 , C23F4/04 , H01L21/302 , H05K3/02 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
摘要： Disclosed is a method of etching a metallized substrate by excimer laser radiation. The substrate is exposed to a selected gas, e.g., a halogen gas, which spontaneously reacts with the metal forming a solid reaction product layer on the metal by a partial consumption of the metal. A beam of radiation from an excimer laser, e.g. XeF laser operating at a wavelength of 351 nm or XeCl laser at 308 nm or KrF laser at 248 nm or KrCl laser at 222 nm or ArF laser at 193 nm or F.sub.2 laser at 157 nm, is applied to the reaction product in a desired pattern to vaporize the reaction product and thereby selectively etch the metal with a high resolution.
摘要翻译： 公开了一种通过准分子激光辐射蚀刻金属化衬底的方法。 将衬底暴露于选定的气体，例如卤素气体，其通过部分消耗金属与金属自发地与金属反应形成固体反应产物层。 来自准分子激光的辐射束，例如， 波长351nm的XeF激光或248nm的KrF激光或222nm的KrCl激光或193nm的ArF激光或157nm的F2激光的XeF激光以期望的图案施加到反应产物 以蒸发反应产物，从而以高分辨率选择性地蚀刻金属。
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10.发明授权Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps 失效在高温步骤期间使用良性可移除栅极材料形成自对准金属栅极FET
公开(公告)号：US5391510A
公开(公告)日：1995-02-21
申请号：US225360
申请日：1994-04-07
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/47 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/28079 , H01L21/28114 , H01L21/28132 , H01L21/28141 , H01L29/42316 , H01L29/47 , H01L29/66545 , H01L29/66659 , Y10S438/945
摘要： A sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions. The source/drain regions are formed by ion implantation using the expendable structure (diamond-like-carbon) as a mask. After the expendable structure has performed its further purpose of protecting the gate dielectric from contamination during the annealing cycle, the structure is easily removed by O.sub.2 plasma and replaced by a conventional metal gate material.
摘要翻译： 公开了一种亚微米FET，其通过使用消耗性自对准栅极结构的方法制造，直到并包括退火源/漏区的步骤。 源极/漏极区域通过使用消耗性结构（类金刚石碳）作为掩模的离子注入形成。 在消耗性结构进一步的目的是在退火循环期间保护栅极电介质免受污染，该结构容易被O 2等离子体去除并被常规的金属栅极材料代替。
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