公开(公告)号：US07781819B2

公开(公告)日：2010-08-24

申请号：US12270286

申请日：2008-11-13

申请人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

发明人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

IPC分类号： H01L29/92

CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L28/60

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括形成在支撑层上并具有接触孔的绝缘层。 第一接触塞形成在接触孔的内壁和底部上。 第二接触插塞将接触孔埋入并形成在第一接触插塞上。 导电层连接到第一接触插塞和第二接触插塞。 形成在接触孔底部的第一接触塞的底部厚度比形成在接触孔的内壁上的第一接触塞的内壁厚度大。

公开(公告)号：US07642148B2

公开(公告)日：2010-01-05

申请号：US11851500

申请日：2007-09-07

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US20060091458A1

公开(公告)日：2006-05-04

申请号：US11265720

申请日：2005-11-02

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Byou-ree Lim

IPC分类号： H01L29/94

CPC分类号： H01L29/66833 ,  H01L29/40117 ,  H01L29/7923

摘要： Provided are a nonvolatile memory device that has enhanced endurance and can accurately read stored data, and a method of manufacturing the same. The nonvolatile memory device includes a trench formed in a semiconductor substrate, a gate electrode formed in the trench, a gate electrode insulating layer interposed between the gate electrode and bottom and lower sidewalls of the trench, a trap structure interposed between upper sidewalls of the trench and the gate electrode and comprising a tunneling layer, a trapping layer, and a blocking layer, and source and drain regions formed on both sides of the semiconductor substrate with respect to the trench, in which the gate electrode insulating layer is not formed and partially overlapped by the trapping layer.

摘要翻译： 提供了具有增强的耐久性并且可以准确地读取存储的数据的非易失性存储器件及其制造方法。 非易失性存储器件包括形成在半导体衬底中的沟槽，形成在沟槽中的栅电极，介于沟槽的栅电极和底侧与下侧壁之间的栅电极绝缘层，夹在沟槽的上侧壁之间的陷阱结构 和栅电极，其包括隧道层，捕获层和阻挡层，以及形成在半导体衬底的相对于沟槽的两侧的源极和漏极区域，其中不形成栅电极绝缘层并且部分地 由捕获层重叠。

公开(公告)号：US20050227432A1

公开(公告)日：2005-10-13

申请号：US11097404

申请日：2005-04-01

申请人： Jae-hyoung Choi ,  Sung-tae Kim ,  Ki-chul Kim ,  Cha-young Yoo ,  Jeong-hee Chung ,  Se-hoon Oh ,  Jeong-sik Choi

发明人： Jae-hyoung Choi ,  Sung-tae Kim ,  Ki-chul Kim ,  Cha-young Yoo ,  Jeong-hee Chung ,  Se-hoon Oh ,  Jeong-sik Choi

IPC分类号： H01L27/108 ,  H01L21/311 ,  H01L21/8242

CPC分类号： H01L21/31122

摘要： A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a meta-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.

摘要翻译： 可以在间绝缘子金属（MIM）型电容器的金属氮化物下电极上形成金属 - 氮氧化物种子电介质层。 金属 - 氮化物种子电介质层可以用作阻挡层，以在例如用于在包括MIM型的集成电路中形成上层金属化/结构的后端处理中减少与金属氮化物下电极的反应 电容器。 包含在金属 - 氮氧化物种子电介质层中的氮可以减少在常规型MIM电容器中可能发生的反应类型。 可以在金属 - 氮化物种子介电层上形成金属氧化物主介电层，并且可以与MIM型电容器中的金属 - 氮化物种子电介质层保持分离。 金属氧化物主电介质层可以被稳定（使用例如热或等离子体处理）以从其中去除缺陷（例如碳）并调整金属氧化物主介电层的化学计量。

公开(公告)号：US06878580B2

公开(公告)日：2005-04-12

申请号：US10341563

申请日：2003-01-13

申请人： Geum-jong Bae ,  Nae-in Lee ,  Ki-chul Kim ,  Hwa-sung Rhee ,  Sang-su Kim ,  Jung-il Lee

发明人： Geum-jong Bae ,  Nae-in Lee ,  Ki-chul Kim ,  Hwa-sung Rhee ,  Sang-su Kim ,  Jung-il Lee

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L29/42376

摘要： A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

摘要翻译： 一种具有负斜率栅极的半导体器件及其制造方法。 形成具有从栅极底部向栅极顶部线性减小的Ge密度分布的多晶硅层，并且通过对多晶硅层进行构图来形成具有负斜率的多晶硅栅极。 通过在图案化时利用Ge密度的蚀刻特性的变化，可以形成底部短于通过光刻限定的顶部的栅极。 因此，门对于短通道器件足够紧凑，并且可以减小栅极电阻。

公开(公告)号：US20100065919A1

公开(公告)日：2010-03-18

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L27/092

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07586137B2

公开(公告)日：2009-09-08

申请号：US11200491

申请日：2005-08-09

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers, a gate insulating layer which is formed on the trapping structure and the exposed semiconductor substrate, a gate electrode which is formed on the gate insulating layer, and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region.

摘要翻译： 提供了具有非对称沟道结构的非易失性存储器件。 非易失性存储器件包括形成在半导体衬底中并掺杂有n型杂质的半导体衬底，源极区和漏极区，包括隧穿层的俘获结构，其被布置在 半导体衬底和通过其电荷载流子被隧道化;以及电荷俘获层，其形成在隧穿层上并俘获隧穿电荷载流子;形成在俘获结构和暴露的半导体衬底上的栅极绝缘层，栅极 形成在栅极绝缘层上的电极和形成在源极区域和漏极区域之间的沟道区域，并且包括形成在捕获结构的下部的第一沟道区域和形成在栅极绝缘层的下部的第二沟道区域 所述第一沟道区的阈值电压低于所述第二沟道区的阈值电压。

公开(公告)号：US20080286927A1

公开(公告)日：2008-11-20

申请号：US12183553

申请日：2008-07-31

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US07396719B2

公开(公告)日：2008-07-08

申请号：US10873256

申请日：2004-06-23

申请人： Kyoung-seok Kim ,  Hong-bae Park ,  Bong-hyun Kim ,  Sung-tae Kim ,  Jong-wan Kwon ,  Jung-hyun Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Gab-jin Nam ,  Young-sun Kim

发明人： Kyoung-seok Kim ,  Hong-bae Park ,  Bong-hyun Kim ,  Sung-tae Kim ,  Jong-wan Kwon ,  Jung-hyun Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Gab-jin Nam ,  Young-sun Kim

IPC分类号： H01L21/471

CPC分类号： H01L21/0228 ,  C23C16/308 ,  C23C16/45531 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3143 ,  H01L21/31645

摘要： A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.

摘要翻译： 使用原子层沉积（ALD）形成高电介质膜的方法以及制造具有高电介质膜的电容器的方法包括将含有金属元素的前体供应到半导体衬底并清洗反应器; 供应氧化剂并清洗反应器; 并供应含氮的反应源并清洗反应器。

公开(公告)号：US07338861B2

公开(公告)日：2008-03-04

申请号：US11109749

申请日：2005-04-20

申请人： Ki-chul Kim ,  Young-cheon Jeong ,  Hyok-ki Kwon

发明人： Ki-chul Kim ,  Young-cheon Jeong ,  Hyok-ki Kwon

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42336

摘要： A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench. An inter-gate insulating layer is formed on the upper portion of floating gate and interposed between the floating gate and the control gate, and a drain region is formed in the surface of the substrate adjacent the control gate and spaced from the second sidewall of the trench.

摘要翻译： 提供一种非易失性存储器件，其包括浮置栅极，该浮置栅极具有形成在衬底表面中的沟槽中的下部，以及从下部突出到衬底表面上方的上部。 栅极绝缘层沿着沟槽的内壁形成并插入在沟槽和浮动栅极的下部之间。 源极区域形成在与沟槽的第一侧壁相邻的衬底中。 具有第一部分的控制栅极形成在邻近沟槽的第二侧壁的衬底的表面上方，并且第二部分形成在浮动栅极的上部并且从第一部分延伸。 沟槽的第一侧壁与沟槽的第二侧壁相对。 栅极间绝缘层形成在浮置栅极的上部并且插入在浮置栅极和控制栅极之间，并且漏极区域形成在基板的与控制栅极相邻的表面中并与第二侧壁间隔开 沟。