公开(公告)号：US20210090629A1

公开(公告)日：2021-03-25

申请号：US16821510

申请日：2020-03-17

Applicant: KIOXIA CORPORATION

Inventor： Kosuke HATSUDA

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: According to one embodiment, a memory device includes first and second wiring lines, a memory cell connected between the first and second wiring lines and including a resistance change memory element and a switching element connected in series to the resistance change memory element, and a determination circuit determining a determination object resistance state set in advance to the resistance change memory element based on a determination object voltage applied to the second wiring line when the switching element makes a transition from an on-state to an off-state.

公开(公告)号：US20210295888A1

公开(公告)日：2021-09-23

申请号：US17201471

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Yoshiaki OSADA ,  Kosuke HATSUDA

IPC: G11C11/16 ,  H01L27/22

Abstract: According to one embodiment, a memory device includes first and second wiring lines, memory cells between first and second wiring lines, first and second common wiring lines, a first selecting circuit between one ends of the first wiring lines and the first common wiring line, and a second selecting circuit between the other ends of the first wiring lines and the first common wiring line. A path between the first wiring line and the first common wiring line through the first selecting circuit and a path between the first wiring line and the first common wiring line through the second selecting circuit are defined as first and second paths, one of the first and second paths is set to an electrically conductive state.

公开(公告)号：US20240304229A1

公开(公告)日：2024-09-12

申请号：US18594104

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Takaya YASUDA ,  Kosuke HATSUDA

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1697

Abstract: A memory system includes a first wiring, a second wiring, a memory cell between the first and second wirings, a first power supply line configured to supply a first voltage, a first transistor between the first power supply line and the first wiring, and configured to supply a current necessary to perform a write operation to the memory cell, a second transistor arranged between the first power supply line and the first wiring, and connected in parallel with the first transistor, a second power supply line configured to supply a second voltage to the second wiring corresponding to the memory cell unselected in the write operation, and a first current copy circuit configured to copy a current flowing to the second power supply line from the second wiring corresponding to the memory cell unselected in the write operation, and configured to control the second transistor based on a copied current.

公开(公告)号：US20240281149A1

公开(公告)日：2024-08-22

申请号：US18645697

申请日：2024-04-25

Applicant: Kioxia Corporation

Inventor： Junji YANO ,  Hidenori MATSUZAKI ,  Kosuke HATSUDA

IPC: G06F3/06 ,  G06F11/14 ,  G06F12/02 ,  G11C7/20 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: G06F3/0619 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0685 ,  G06F11/1456 ,  G06F11/1471 ,  G06F12/0246 ,  G11C7/20 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/105 ,  G06F11/1469 ,  G06F2201/84 ,  G06F2212/7201 ,  G06F2212/7207

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

公开(公告)号：US20240361915A1

公开(公告)日：2024-10-31

申请号：US18765095

申请日：2024-07-05

Applicant: KIOXIA CORPORATION

Inventor： Junji YANO ,  Hidenori MATSUZAKI ,  Kosuke HATSUDA

IPC: G06F3/06 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G11C29/00 ,  G11C29/04

CPC classification number: G06F3/0614 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/073 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G11C29/88 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/22 ,  G06F2212/7202 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

公开(公告)号：US20240321334A1

公开(公告)日：2024-09-26

申请号：US18595065

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Kosuke HATSUDA

IPC: G11C11/16 ,  G11C29/12

CPC classification number: G11C11/1653 ,  G11C29/12005 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: According to one embodiment, there is provided a storage device comprising a first memory chip that includes a plurality of first memory cells and that includes a first circuit configured to perform address conversion by using a conversion function; and a second circuit that is connected to the first memory chip and that is configured to set a first parameter for the first memory chip, wherein when a first address is transmitted to the first memory chip from the second circuit, the first address is converted into a second address by the conversion function using the first parameter, and then one of the plurality of first memory cells that corresponds to the second address in the first memory chip is accessed.

公开(公告)号：US20230410853A1

公开(公告)日：2023-12-21

申请号：US18178135

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Akira KATAYAMA ,  Kosuke HATSUDA

IPC: G11C7/06 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C7/067 ,  G11C7/1069 ,  G11C5/063

Abstract: A memory system according to an embodiment includes a plurality of first wirings, a plurality of second wirings, a memory cell, a third wiring, a sense amplifier, a first switching element, a first transistor including a first terminal connected to a first node and a second terminal connected to a second node, and a control circuit. The first node is positioned further to the side of the sense amplifier than the first switching element. The second node is positioned further to the memory cell than the first switching element. The control circuit is configured to connect the first node and the second node when the first switching element is in an ON state, and connect the first node and the gate terminal of the first transistor when the first switching element is in an OFF state.

公开(公告)号：US20230297258A1

公开(公告)日：2023-09-21

申请号：US17939848

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Kosuke HATSUDA

IPC: G06F3/06 ,  G11C11/16

CPC classification number: G06F3/0632 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673

Abstract: A memory system includes a non-volatile memory and a memory controller configured to receive a command including an access target in the non-volatile memory and setting information from an external device and configured to control a writing operation or a reading operation to the access target. The memory controller has a condition setting circuit. The condition setting circuit is capable of performing the writing operation or the reading operation under a plurality of different conditions. The memory controller performs the writing operation or the reading operation under one of the plurality of different conditions selected by the condition setting circuit in accordance with the setting information.

公开(公告)号：US20220093148A1

公开(公告)日：2022-03-24

申请号：US17350382

申请日：2021-06-17

Applicant: Kioxia Corporation

Inventor： Kosuke HATSUDA

IPC: G11C11/16 ,  G11C7/10

Abstract: In a memory, a first node holds first data from a first cell. A second node holds second data from a second cell near the first cell. A differential circuit includes a first current path passing a first current corresponding to a voltage of the first node and a second current path passing a second current corresponding to a voltage of the second node, and outputs an output signal corresponding to a voltage difference between the first and the second nodes from an output part. A first register latches the output signal and output the signal as a hold signal. A first offset part is connected to the first current path and offsets the first current when the hold signal has a first logic level. A second offset part is connected to the second current path and offsets the second current when the hold signal has a second logic level.

公开(公告)号：US20240428837A1

公开(公告)日：2024-12-26

申请号：US18749367

申请日：2024-06-20

Applicant: Kioxia Corporation

Inventor： Kosuke HATSUDA

IPC: G11C11/16 ,  G11C5/06

Abstract: A memory device includes a first wiring, a second wiring, a memory cell connected between the first wiring and the second wiring, a first power line, a sense amplifier, a current control circuit provided between the first power line and the sense amplifier and including a control terminal connected to a first node, a capacitance element provided between the first node and the second wiring and including a first terminal electrically connected to the second wiring and a second terminal connected to the first node, a second power line, and a first element having an electrical resistance provided between the first node and the second power line.