公开(公告)号：US06171905B2

公开(公告)日：2001-01-09

申请号：US09192537

申请日：1998-11-17

申请人： Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Koichiro Yuki ,  Kiyoshi Araki

发明人： Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Koichiro Yuki ,  Kiyoshi Araki

IPC分类号： H01L21336

CPC分类号： H01L21/76264 ,  H01L21/76267 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/7606 ,  H01L29/882

摘要： The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO2 type quantum device can be manufactured with ease at a low cost.

摘要翻译： 本发明提供一种半导体器件，其具有各种功能，例如双稳态存储器和逻辑电路，其中在公共衬底上形成有MOS半导体元件，谐振隧道二极管，热电子晶体管等。 在SOI衬底上形成由隔离氧化膜包围的n型Si层和p型Si层。 形成掩模氧化膜和栅极氧化膜，并且通过使用掩模氧化膜作为掩模对n型Si层进行结晶各向异性蚀刻，以将n型Si层改变为 薄Si板。 在该n型Si层的侧面上形成第一和第二隧道氧化物膜之后，共用隧道二极管的第一和第二多晶硅电极和用作MOS半导体元件的栅电极的多晶硅电极由共同的 多晶硅膜。 因此，可以容易地以低成本制造Si / SiO 2型量子器件。

公开(公告)号：US6091077A

公开(公告)日：2000-07-18

申请号：US955267

申请日：1997-10-21

申请人： Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Koichiro Yuki ,  Kiyoshi Araki

发明人： Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Koichiro Yuki ,  Kiyoshi Araki

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/88 ,  H01L29/06

CPC分类号： H01L21/76264 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/7606 ,  H01L29/882 ,  H01L21/76267 ,  H01L21/76281

摘要： The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO.sub.2 type quantum device can be manufactured with ease at a low cost.

摘要翻译： 本发明提供一种半导体器件，其具有各种功能，例如双稳态存储器和逻辑电路，其中在公共衬底上形成有MOS半导体元件，谐振隧道二极管，热电子晶体管等。 在SOI衬底上形成由隔离氧化膜包围的n型Si层和p型Si层。 形成掩模氧化膜和栅极氧化膜，并且通过使用掩模氧化膜作为掩模对n型Si层进行结晶各向异性蚀刻，以将n型Si层改变为 薄Si板。 在该n型Si层的侧面上形成第一和第二隧道氧化物膜之后，共用隧道二极管的第一和第二多晶硅电极和用作MOS半导体元件的栅电极的多晶硅电极由共同的 多晶硅膜。 因此，可以容易地以低成本制造Si / SiO 2型量子器件。

公开(公告)号：US06303516B1

公开(公告)日：2001-10-16

申请号：US09208753

申请日：1998-12-10

申请人： Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Kiyoshi Araki ,  Koichiro Yuki ,  Kazuyasu Adachi ,  Masayuki Endo ,  Ichiro Yamashita

发明人： Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Kiyoshi Araki ,  Koichiro Yuki ,  Kazuyasu Adachi ,  Masayuki Endo ,  Ichiro Yamashita

IPC分类号： H01L2146

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5671 ,  G11C13/0019 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/288 ,  H01L21/768 ,  H01L29/7883 ,  Y10S438/962

摘要： A Rat IgG antibody film, formed on a p-type Si substrate, is selectively irradiated with ultraviolet rays, thereby leaving part of the Rat IgG antibody film, except for a region deactivated with the ultraviolet rays. Next, when the p-type Si substrate is immersed in a solution containing Au fine particles that have been combined with a Rat IgG antigen, the Rat IgG antigen is selectively combined with the Rat IgG antibody film. As a result, Au fine particles, combined with the Rat IgG antigen, are fixed on the Rat IgG antibody film. Thereafter, the p-type Si substrate is placed within oxygen plasma for 20 minutes, thereby removing the Rat IgG antibody film, the deactivated Rat IgG antibody film and the Rat IgG antigen. Consequently, dot elements can be formed at desired positions on the p-type Si substrate. If these dot elements are used for the floating gate of a semiconductor memory device, then the device has a structure suitable for miniaturization.

摘要翻译： 在p型Si衬底上形成的大鼠IgG抗体膜被紫外线选择性照射，除了用紫外线去活化的区域外，还剩下部分IgG抗体。 接下来，当将p型Si衬底浸入含有与大鼠IgG抗原组合的Au微粒的溶液中时，将大鼠IgG抗原与大鼠IgG抗体膜选择性组合。 结果，将Au细粒与大鼠IgG抗原组合，固定在大鼠IgG抗体膜上。 此后，将p型Si衬底置于氧等离子体中20分钟，从而除去大鼠IgG抗体膜，失活的大鼠IgG抗体膜和大鼠IgG抗原。 因此，可以在p型Si衬底上的期望位置形成点元件。 如果这些点元件用于半导体存储器件的浮动栅极，则该器件具有适于小型化的结构。

公开(公告)号：US06342716B1

公开(公告)日：2002-01-29

申请号：US09320695

申请日：1999-05-27

申请人： Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Kiyoshi Araki ,  Koichiro Yuki ,  Kazuyasu Adachi ,  Masayuki Endo ,  Ichiro Yamashita

发明人： Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Kiyoshi Araki ,  Koichiro Yuki ,  Kazuyasu Adachi ,  Masayuki Endo ,  Ichiro Yamashita

IPC分类号： H01L29788

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5671 ,  G11C13/0019 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/288 ,  H01L21/768 ,  H01L29/7883 ,  Y10S438/962

摘要： A semiconductor device as a nonvolatile memory comprises dot elements which are formed out of the semiconductor or conductor fine particles and function as a floating gate. The dot elements are asymmetrically formed to a control gate and may be formed in a sidewall insulating film formed over the side face of the control gate or a select gate. When inclined or stepped portions having level differences are formed in a semiconductor substrate, the dot elements are formed on a specified portion of the inclined or stepped portions.

摘要翻译： 作为非易失性存储器的半导体器件包括由半导体或导体细颗粒形成并作为浮栅的功能的点元件。 点元件与控制栅极不对称地形成，并且可以形成在形成在控制栅极或选择栅极的侧面上的侧壁绝缘膜中。 当在半导体衬底中形成具有电平差的倾斜或阶梯部分时，点元素形成在倾斜或阶梯部分的特定部分上。

公开(公告)号：US5972744A

公开(公告)日：1999-10-26

申请号：US37016

申请日：1998-03-09

申请人： Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Kiyoshi Araki ,  Yoshihiko Hirai ,  Koichiro Yuki

发明人： Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Kiyoshi Araki ,  Yoshihiko Hirai ,  Koichiro Yuki

IPC分类号： H01L21/335 ,  H01L29/775 ,  H01L21/70

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/66439

摘要： A silicon island portion is formed in a quantum wire so as to be sandwiched between a pair of tunnel barrier portions of a silicon oxide film. On one side of the silicon island portion, a gate electrode for potential control is disposed with a gate insulating film of a silicon oxide film interposed therebetween. On the other side of the silicon island portion, a control electrode for potential control is disposed with an insulating film of a silicon oxide film interposed therebetween. Each of the tunnel barrier portions has a quantum wire constriction structure, which is formed by oxidizing a quantum wire, i.e., a silicon oxide film formed as a field enhanced oxide film with an atomic force microscope or the like, from its surface to a substantially center portion in its section.

摘要翻译： 硅岛部分形成在量子线中，以夹在氧化硅膜的一对隧道势垒部分之间。 在硅岛部分的一侧，用于电位控制的栅电极设置有介于其间的氧化硅膜的栅极绝缘膜。 在硅岛部分的另一侧，用于电位控制的控制电极设置有隔着氧化硅膜的绝缘膜。 每个隧道势垒部分具有量子线收缩结构，该量子线收缩结构通过使用原子力显微镜等将形成为场增强氧化物膜的量子线，即其表面氧化成基本上 中心部分在其部分。

公开(公告)号：US6015978A

公开(公告)日：2000-01-18

申请号：US175505

申请日：1998-10-20

申请人： Koichiro Yuki ,  Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Yoshihiko Hirai

发明人： Koichiro Yuki ,  Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Yoshihiko Hirai

IPC分类号： H01L21/306 ,  H01L21/329 ,  H01L29/88 ,  H01L29/06

CPC分类号： H01L29/6609 ,  H01L21/30608 ,  H01L29/882 ,  Y10S438/962

摘要： The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.

摘要翻译： 形成本发明的半导体微结构的方法包括以下步骤：在具有半导体层作为其上部的衬底上形成具有第一开口和第二开口的掩模图案; 以及使用所述掩模图案选择性地蚀刻所述半导体层，以形成在平行于所述基板的表面的第一方向上延伸的半导体微结构，其中，在选择性地蚀刻所述半导体层的步骤中，沿垂直于所述基板的第二方向的蚀刻速率 第一方向并平行于衬底的表面相对于第一方向上的蚀刻速率基本上为零，并且半导体微结构的宽度基本上等于第一开口和第二开口在第二方向上的最短距离 。

公开(公告)号：US5888852A

公开(公告)日：1999-03-30

申请号：US808580

申请日：1997-02-28

申请人： Koichiro Yuki ,  Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Yoshihiko Hirai

发明人： Koichiro Yuki ,  Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Yoshihiko Hirai

IPC分类号： H01L21/306 ,  H01L21/329 ,  H01L29/88 ,  H01L21/20

CPC分类号： H01L29/6609 ,  H01L21/30608 ,  H01L29/882 ,  Y10S438/962

摘要： The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.

摘要翻译： 形成本发明的半导体微结构的方法包括以下步骤：在具有半导体层作为其上部的衬底上形成具有第一开口和第二开口的掩模图案; 以及使用所述掩模图案选择性地蚀刻所述半导体层，以形成在平行于所述基板的表面的第一方向上延伸的半导体微结构，其中，在选择性地蚀刻所述半导体层的步骤中，沿垂直于所述基板的第二方向的蚀刻速率 第一方向并平行于衬底的表面相对于第一方向上的蚀刻速率基本上为零，并且半导体微结构的宽度基本上等于第一开口和第二开口在第二方向上的最短距离 。

公开(公告)号：US6103583A

公开(公告)日：2000-08-15

申请号：US370005

申请日：1999-08-06

申请人： Kiyoshi Morimoto ,  Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoyuki Morita

发明人： Kiyoshi Morimoto ,  Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoyuki Morita

IPC分类号： H01L21/329 ,  H01L27/10 ,  H01L27/12 ,  H01L29/88 ,  H01L21/331

CPC分类号： H01L29/66151 ,  H01L27/10 ,  H01L27/1203 ,  H01L29/882

摘要： A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.

摘要翻译： 量化功能器件包括：具有由预定晶体表面制成的第一表面和第二表面的硅薄层，并且所述硅薄层由厚度足够薄以用作量子阱的单晶硅形成; 分别设置在所述硅薄层的所述第一表面和所述第二表面上的一对隧道屏障; 以及第一电极和第二电极，其可操作地彼此耦合并且形成为将硅薄层和所述一对隧道屏障插入其间。

公开(公告)号：US5945687A

公开(公告)日：1999-08-31

申请号：US757578

申请日：1996-11-27

申请人： Kiyoshi Morimoto ,  Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoyuki Morita

发明人： Kiyoshi Morimoto ,  Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoyuki Morita

IPC分类号： H01L21/329 ,  H01L27/10 ,  H01L27/12 ,  H01L29/88 ,  H01L29/06

CPC分类号： H01L29/66151 ,  H01L27/10 ,  H01L27/1203 ,  H01L29/882

摘要： A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.

摘要翻译： 量化功能器件包括：具有由预定晶体表面制成的第一表面和第二表面的硅薄层，并且所述硅薄层由厚度足够薄以用作量子阱的单晶硅形成; 分别设置在所述硅薄层的所述第一表面和所述第二表面上的一对隧道屏障; 以及第一电极和第二电极，其可操作地彼此耦合并且形成为将硅薄层和所述一对隧道屏障插入其间。

公开(公告)号：US5739544A

公开(公告)日：1998-04-14

申请号：US571112

申请日：1995-12-12

申请人： Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa ,  Kiyoyuki Morita

发明人： Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa ,  Kiyoyuki Morita

IPC分类号： H01L21/329 ,  H01L29/04 ,  H01L29/76 ,  H01L29/88 ,  H01L29/78

CPC分类号： B82Y10/00 ,  H01L29/045 ,  H01L29/66151 ,  H01L29/7606 ,  H01L29/882

摘要： By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a resonance tunneling transistor.

摘要翻译： 通过蚀刻，在硅衬底中形成第一凹槽和第二凹槽。 这些凹槽的侧壁的表面具有（111）的表面取向。 第一和第二沟槽夹在其间的硅薄板，其形成为硅衬底的一部分。 硅薄板足够薄，以作为量子阱。 此外，在硅薄板的侧壁的表面上形成用作隧道势垒的一对氧化硅膜，从而形成双重阻挡结构。 此外，形成一对多晶硅电极并夹着双重阻挡结构。 结果，提供了利用谐振隧穿效应的共振隧道二极管的结构。 向上述结构添加第三电极提供谐振隧穿晶体管。