公开(公告)号：US6015978A

公开(公告)日：2000-01-18

申请号：US175505

申请日：1998-10-20

申请人： Koichiro Yuki ,  Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Yoshihiko Hirai

发明人： Koichiro Yuki ,  Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Yoshihiko Hirai

IPC分类号： H01L21/306 ,  H01L21/329 ,  H01L29/88 ,  H01L29/06

CPC分类号： H01L29/6609 ,  H01L21/30608 ,  H01L29/882 ,  Y10S438/962

摘要： The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.

摘要翻译： 形成本发明的半导体微结构的方法包括以下步骤：在具有半导体层作为其上部的衬底上形成具有第一开口和第二开口的掩模图案; 以及使用所述掩模图案选择性地蚀刻所述半导体层，以形成在平行于所述基板的表面的第一方向上延伸的半导体微结构，其中，在选择性地蚀刻所述半导体层的步骤中，沿垂直于所述基板的第二方向的蚀刻速率 第一方向并平行于衬底的表面相对于第一方向上的蚀刻速率基本上为零，并且半导体微结构的宽度基本上等于第一开口和第二开口在第二方向上的最短距离 。

公开(公告)号：US5888852A

公开(公告)日：1999-03-30

申请号：US808580

申请日：1997-02-28

申请人： Koichiro Yuki ,  Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Yoshihiko Hirai

发明人： Koichiro Yuki ,  Kiyoyuki Morita ,  Kiyoshi Morimoto ,  Yoshihiko Hirai

IPC分类号： H01L21/306 ,  H01L21/329 ,  H01L29/88 ,  H01L21/20

CPC分类号： H01L29/6609 ,  H01L21/30608 ,  H01L29/882 ,  Y10S438/962

摘要： The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.

摘要翻译： 形成本发明的半导体微结构的方法包括以下步骤：在具有半导体层作为其上部的衬底上形成具有第一开口和第二开口的掩模图案; 以及使用所述掩模图案选择性地蚀刻所述半导体层，以形成在平行于所述基板的表面的第一方向上延伸的半导体微结构，其中，在选择性地蚀刻所述半导体层的步骤中，沿垂直于所述基板的第二方向的蚀刻速率 第一方向并平行于衬底的表面相对于第一方向上的蚀刻速率基本上为零，并且半导体微结构的宽度基本上等于第一开口和第二开口在第二方向上的最短距离 。

公开(公告)号：US5972744A

公开(公告)日：1999-10-26

申请号：US37016

申请日：1998-03-09

申请人： Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Kiyoshi Araki ,  Yoshihiko Hirai ,  Koichiro Yuki

发明人： Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Kiyoshi Araki ,  Yoshihiko Hirai ,  Koichiro Yuki

IPC分类号： H01L21/335 ,  H01L29/775 ,  H01L21/70

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/66439

摘要： A silicon island portion is formed in a quantum wire so as to be sandwiched between a pair of tunnel barrier portions of a silicon oxide film. On one side of the silicon island portion, a gate electrode for potential control is disposed with a gate insulating film of a silicon oxide film interposed therebetween. On the other side of the silicon island portion, a control electrode for potential control is disposed with an insulating film of a silicon oxide film interposed therebetween. Each of the tunnel barrier portions has a quantum wire constriction structure, which is formed by oxidizing a quantum wire, i.e., a silicon oxide film formed as a field enhanced oxide film with an atomic force microscope or the like, from its surface to a substantially center portion in its section.

摘要翻译： 硅岛部分形成在量子线中，以夹在氧化硅膜的一对隧道势垒部分之间。 在硅岛部分的一侧，用于电位控制的栅电极设置有介于其间的氧化硅膜的栅极绝缘膜。 在硅岛部分的另一侧，用于电位控制的控制电极设置有隔着氧化硅膜的绝缘膜。 每个隧道势垒部分具有量子线收缩结构，该量子线收缩结构通过使用原子力显微镜等将形成为场增强氧化物膜的量子线，即其表面氧化成基本上 中心部分在其部分。

公开(公告)号：US5739544A

公开(公告)日：1998-04-14

申请号：US571112

申请日：1995-12-12

申请人： Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa ,  Kiyoyuki Morita

发明人： Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa ,  Kiyoyuki Morita

IPC分类号： H01L21/329 ,  H01L29/04 ,  H01L29/76 ,  H01L29/88 ,  H01L29/78

CPC分类号： B82Y10/00 ,  H01L29/045 ,  H01L29/66151 ,  H01L29/7606 ,  H01L29/882

摘要： By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a resonance tunneling transistor.

摘要翻译： 通过蚀刻，在硅衬底中形成第一凹槽和第二凹槽。 这些凹槽的侧壁的表面具有（111）的表面取向。 第一和第二沟槽夹在其间的硅薄板，其形成为硅衬底的一部分。 硅薄板足够薄，以作为量子阱。 此外，在硅薄板的侧壁的表面上形成用作隧道势垒的一对氧化硅膜，从而形成双重阻挡结构。 此外，形成一对多晶硅电极并夹着双重阻挡结构。 结果，提供了利用谐振隧穿效应的共振隧道二极管的结构。 向上述结构添加第三电极提供谐振隧穿晶体管。

公开(公告)号：US6103583A

公开(公告)日：2000-08-15

申请号：US370005

申请日：1999-08-06

申请人： Kiyoshi Morimoto ,  Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoyuki Morita

发明人： Kiyoshi Morimoto ,  Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoyuki Morita

IPC分类号： H01L21/329 ,  H01L27/10 ,  H01L27/12 ,  H01L29/88 ,  H01L21/331

CPC分类号： H01L29/66151 ,  H01L27/10 ,  H01L27/1203 ,  H01L29/882

摘要： A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.

摘要翻译： 量化功能器件包括：具有由预定晶体表面制成的第一表面和第二表面的硅薄层，并且所述硅薄层由厚度足够薄以用作量子阱的单晶硅形成; 分别设置在所述硅薄层的所述第一表面和所述第二表面上的一对隧道屏障; 以及第一电极和第二电极，其可操作地彼此耦合并且形成为将硅薄层和所述一对隧道屏障插入其间。

公开(公告)号：US5945687A

公开(公告)日：1999-08-31

申请号：US757578

申请日：1996-11-27

申请人： Kiyoshi Morimoto ,  Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoyuki Morita

发明人： Kiyoshi Morimoto ,  Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoyuki Morita

IPC分类号： H01L21/329 ,  H01L27/10 ,  H01L27/12 ,  H01L29/88 ,  H01L29/06

CPC分类号： H01L29/66151 ,  H01L27/10 ,  H01L27/1203 ,  H01L29/882

摘要： A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.

摘要翻译： 量化功能器件包括：具有由预定晶体表面制成的第一表面和第二表面的硅薄层，并且所述硅薄层由厚度足够薄以用作量子阱的单晶硅形成; 分别设置在所述硅薄层的所述第一表面和所述第二表面上的一对隧道屏障; 以及第一电极和第二电极，其可操作地彼此耦合并且形成为将硅薄层和所述一对隧道屏障插入其间。

公开(公告)号：US5486706A

公开(公告)日：1996-01-23

申请号：US249541

申请日：1994-05-26

申请人： Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa

发明人： Koichiro Yuki ,  Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa

IPC分类号： H01L21/329 ,  H01L29/04 ,  H01L29/76 ,  H01L29/88 ,  H01L31/036

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/66151 ,  H01L29/7606 ,  H01L29/882 ,  Y10S438/962 ,  Y10S438/979

摘要： By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a hot electron transistor. In the quantization functional devices having the above-described configuration, the satisfactory resonance effect is obtained due to a high crystallinity of the quantum well, a high potential barrier brought by the high quality silicon oxide films used as the tunneling barriers and a smooth interface between the quantum well and the tunneling barriers.

摘要翻译： 通过蚀刻，在硅衬底中形成第一凹槽和第二凹槽。 这些凹槽的侧壁的表面具有（111）的表面取向。 第一和第二沟槽夹在其间的硅薄板，其形成为硅衬底的一部分。 硅薄板足够薄，以作为量子阱。 此外，在硅薄板的侧壁的表面上形成用作隧道势垒的一对氧化硅膜，从而形成双重阻挡结构。 此外，形成一对多晶硅电极并夹着双重阻挡结构。 结果，提供了利用谐振隧穿效应的共振隧道二极管的结构。 向上述结构添加第三电极提供热电子晶体管。 在具有上述结构的量子化功能器件中，由于量子阱的高结晶度，由用作隧道势垒的高质量氧化硅膜引起的高电位势垒和由于量子阱的高结晶度而产生令人满意的共振效应， 量子阱和隧道势垒。

公开(公告)号：US5562802A

公开(公告)日：1996-10-08

申请号：US419179

申请日：1995-04-10

申请人： Kenji Okada ,  Kiyoshi Morimoto ,  Masaharu Udagawa ,  Koichiro Yuki ,  Masaaki Niwa ,  Yoshihiko Hirai ,  Juro Yasui

发明人： Kenji Okada ,  Kiyoshi Morimoto ,  Masaharu Udagawa ,  Koichiro Yuki ,  Masaaki Niwa ,  Yoshihiko Hirai ,  Juro Yasui

IPC分类号： H01L29/06 ,  H01L21/334 ,  H01L29/10 ,  H01L29/68 ,  H01L29/772 ,  H01L29/88 ,  B44C1/22 ,  C03C15/00 ,  H01L29/161

CPC分类号： B82Y10/00 ,  B82Y30/00 ,  H01L29/1037 ,  H01L29/66931 ,  H01L29/772 ,  H01L29/882 ,  Y10S438/911 ,  Y10S438/962

摘要： A quantum device including a plate-like conductor part having a necking portion and a method of producing the same are disclosed. The method includes the steps of forming a first mask layer having a first strip portion on a conductor substrate; forming a second mask layer having a second strip portion on the conductor substrate; etching a region of the conductor substrate which is not covered with the first and second mask layers, by using the first and second mask layers as an etching mask, to form a plurality of first recess portions on a surface of the conductor substrate; selectively covering side faces of the plurality of first recess portions, and side faces of the first and second mask layers with a side wall film; selectively removing only the second mask layer, the first mask layer and the side wall film being left unremoved; etching another region of the conductor substrate which is not covered with the first mask layer and the side wall film, by using the first mask layer and the side wall film as an etching mask, to form a plurality of second recess portions on the surface of the conductor substrate; selectively removing part of another region of the surface of the conductor substrate which is not covered with the first mask layer and the side wall film; and removing the first mask layer and the side wall film, to form the plate-like conductor part having the necking portion at the conductor substrate.

摘要翻译： 公开了一种包括具有颈缩部的板状导体部的量子装置及其制造方法。 该方法包括以下步骤：在导体基板上形成具有第一条带部分的第一掩模层; 在所述导体基板上形成具有第二带状部分的第二掩模层; 通过使用第一和第二掩模层作为蚀刻掩模蚀刻未被第一和第二掩模层覆盖的导体基板的区域，以在导体基板的表面上形成多个第一凹部; 选择性地覆盖所述多个第一凹部的侧面，所述第一和第二掩模层的侧面具有侧壁膜; 仅选择性地除去第二掩模层，第一掩模层和侧壁膜不被去除; 通过使用第一掩模层和侧壁膜作为蚀刻掩模蚀刻未被第一掩模层和侧壁膜覆盖的导体基板的另一区域，以在第一掩模层和侧壁膜的表面上形成多个第二凹部 导体基板; 选择性地去除未被第一掩模层和侧壁膜覆盖的导体基板的表面的另一区域的一部分; 并且去除第一掩模层和侧壁膜，以在导体基板上形成具有颈缩部分的板状导体部分。

公开(公告)号：US5543351A

公开(公告)日：1996-08-06

申请号：US331733

申请日：1994-10-31

申请人： Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Yasuaki Terui ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa ,  Koichiro Yuki

发明人： Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Yasuaki Terui ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa ,  Koichiro Yuki

IPC分类号： H01L21/335 ,  H01L29/04 ,  H01L21/76

CPC分类号： B82Y10/00 ,  H01L29/045 ,  H01L29/66439 ,  Y10S438/962

摘要： A silicon substrate comprises at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from the surfaces, and an electrically conductive portion insulated electrically by the electrically insulating layer from an outside of the silicon substrate.

摘要翻译： 硅衬底包括至少两个表面，所述至少两个表面基本上沿着硅的（111）晶体取向的晶面延伸，（111）晶体取向的晶面相互交叉，通过将硅衬底从 表面，以及由电绝缘层与硅衬底的外部电绝缘的导电部分。

公开(公告)号：US5405454A

公开(公告)日：1995-04-11

申请号：US30556

申请日：1993-03-12

申请人： Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Yasuaki Terui ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa ,  Koichiro Yuki

发明人： Yoshihiko Hirai ,  Kiyoshi Morimoto ,  Yasuaki Terui ,  Masaaki Niwa ,  Juro Yasui ,  Kenji Okada ,  Masaharu Udagawa ,  Koichiro Yuki

IPC分类号： H01L21/335 ,  H01L29/04 ,  H01L29/30

CPC分类号： B82Y10/00 ,  H01L29/045 ,  H01L29/66439 ,  Y10S438/962

摘要： A silicon substrate comprises, at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from the surfaces, and an electrically conductive portion insulated electrically by the electrically insulating layer from an outside of the silicon substrate.

摘要翻译： 硅衬底包括至少两个表面，其基本上沿着硅的（111）晶体取向的晶面延伸，（111）晶体取向的晶面相互交叉，通过将硅衬底氧化从而形成的电绝缘层 表面和由电绝缘层与硅衬底的外部电绝缘的导电部分。