公开(公告)号：US5227658A

公开(公告)日：1993-07-13

申请号：US781429

申请日：1991-10-23

申请人： Klaus D. Beyer ,  San-Mei Ku ,  Victor J. Silvestri ,  Andrie S. Yapsir

发明人： Klaus D. Beyer ,  San-Mei Ku ,  Victor J. Silvestri ,  Andrie S. Yapsir

IPC分类号： H01L21/76 ,  H01L21/764 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/764

摘要： A method for isolating areas of silicon from a substrate 50 includes the steps of: providing a buried N+ region 52 in the substrate; forming an intrinsic epitaxial layer 12 onto the N+ region; etching trenches 18, 20 through the intrinsic epitaxial layer to thereby form a desired isolation region 16 of intrinsic epitaxial material; laterally etching a cavity 22 underneath the desired isolation region; and, forming an insulation layer 24 of insulation material along the bottom of the desired isolation region exposed by the former etching steps.

公开(公告)号：US5234535A

公开(公告)日：1993-08-10

申请号：US988655

申请日：1992-12-10

申请人： Klaus D. Beyer ,  Louis L. Hsu ,  Victor J. Silvestri ,  Andrie S. Yapsir

发明人： Klaus D. Beyer ,  Louis L. Hsu ,  Victor J. Silvestri ,  Andrie S. Yapsir

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/762

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/981

摘要： A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed. The method comprises the steps of:a) providing a first wafer comprising a silicon substrate of a first conductivity type, a diffusion layer of a second conductivity type formed thereon and having a first etch characteristic, a thin epitaxial layer of the second conductivity type formed upon the diffusion layer and having a second etch characteristic different from the first etch characteristic of the diffusion layer, and a thin oxide layer formed upon the thin epitaxial layer;b) providing a second wafer comprising a silicon substrate having a thin oxide layer formed on a surface thereof;c) wafer bonding said first wafer to said second wafer;d) removing the silicon substrate of said first wafer in a controlled mechanical manner; ande) removing the diffusion layer of said first wafer using a selective dry low energy plasma process to expose the underlying thin epitaxial layer, the selective dry low energy plasma process providing an etch ratio of the first etch characteristic to the second etch characteristic such that the diffusion layer is removed with minimal formation of any shallow plasma radiation damage to the exposed underlying thin epitaxial layer.

公开(公告)号：US5232866A

公开(公告)日：1993-08-03

申请号：US781437

申请日：1991-10-23

申请人： Klaus D. Beyer ,  Victor J. Silvestri ,  Andrie S. Yapsir

发明人： Klaus D. Beyer ,  Victor J. Silvestri ,  Andrie S. Yapsir

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/764 ,  H01L21/7682

摘要： A method for isolating a film from a substrate 50 includes the steps of: providing an N+ layer 52 on the substrate 50; forming an insulation layer 54 onto the N+ doped layer 52; etching a pair of trenches 56, 58 through the insulation layer 52 to thereby form an isolation region 60 of insulation material; laterally etching a cavity 62 underneath the isolation region; and, forming a film 64 onto the isolation region.

公开(公告)号：US4528047A

公开(公告)日：1985-07-09

申请号：US624425

申请日：1984-06-25

申请人： Klaus D. Beyer ,  Victor J. Silvestri

发明人： Klaus D. Beyer ,  Victor J. Silvestri

IPC分类号： H01L21/76 ,  H01L21/20 ,  H01L21/74 ,  H01L21/763 ,  H01L21/302

CPC分类号： H01L21/743 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/763 ,  Y10S148/025 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/085

摘要： A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer. A second insulating layer is located on the polycrystalline silicon layer within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer above the epitaxial layer completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.

摘要翻译： 描述了一种无空隙的隔离半导体衬底，其包含半导体本体内的基本上垂直的沟槽的图案。 隔离沟槽的图案隔离可能包含有源和无源半导体器件的单晶半导体材料的区域。 第一绝缘层位于沟槽的侧壁上。 沟槽的底部或底部对单晶半导体体是开放的。 从沟槽的底部延伸的外延层将沟槽的图案从沟槽的上表面填充到高达一定水平，如以下等式所规定的：y = 0.34x其中y是外延层和顶表面之间的距离 x是沟槽宽度。 沟槽宽度x的优选范围为约10微米或更小。 多晶硅层填充在外延层的上表面上方的沟槽图案的附加部分。 第二绝缘层位于沟槽内的多晶硅层上，用于隔离沟槽图案与环境。 密封的外延单晶半导体防止在沟槽图案内形成空隙。 外延层上方的多晶硅层完全覆盖外延半导体生长结构顶部的不期望的尖锐刻面结构。

公开(公告)号：US4758531A

公开(公告)日：1988-07-19

申请号：US111888

申请日：1987-10-23

申请人： Klaus D. Beyer ,  Louis L. Hsu ,  Dominic J. Schepis ,  Victor J. Silvestri

发明人： Klaus D. Beyer ,  Louis L. Hsu ,  Dominic J. Schepis ,  Victor J. Silvestri

IPC分类号： H01L21/205 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76294 ,  Y10S148/026 ,  Y10S148/029 ,  Y10S148/097

摘要： A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.

公开(公告)号：US4745081A

公开(公告)日：1988-05-17

申请号：US793518

申请日：1985-10-31

申请人： Klaus D. Beyer ,  Victor J. Silvestri

发明人： Klaus D. Beyer ,  Victor J. Silvestri

IPC分类号： H01L21/76 ,  H01L21/225 ,  H01L21/74 ,  H01L21/763 ,  H01L29/41 ,  H01L21/36 ,  H01L21/425

CPC分类号： H01L21/763 ,  H01L21/2255 ,  H01L21/743

摘要： A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

公开(公告)号：US4680614A

公开(公告)日：1987-07-14

申请号：US711554

申请日：1985-03-14

申请人： Klaus D. Beyer ,  Victor J. Silvestri

发明人： Klaus D. Beyer ,  Victor J. Silvestri

IPC分类号： H01L21/20 ,  H01L21/74 ,  H01L21/763 ,  H01L21/95 ,  H01L27/04

CPC分类号： H01L21/743 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/763 ,  Y10S148/05 ,  Y10S148/085 ,  Y10S148/122 ,  Y10S148/131

摘要： A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer. A second insulating layer is located on the polycrystalline silicon layer within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer above the epitaxial layer completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.

摘要翻译： 描述了一种无空隙的隔离半导体衬底，其包含半导体本体内的基本上垂直的沟槽的图案。 隔离沟槽的图案隔离可能包含有源和无源半导体器件的单晶半导体材料的区域。 第一绝缘层位于沟槽的侧壁上。 沟槽的底部或底部对单晶半导体体是开放的。 从沟槽的底部延伸的外延层将沟槽的图案从沟槽的上表面填充到高达一定水平，如以下等式所规定的：y = 0.34x其中y是外延层和顶表面之间的距离 x是沟槽宽度。 沟槽宽度x的优选范围为约10微米或更小。 多晶硅层填充在外延层的上表面上方的沟槽图案的附加部分。 第二绝缘层位于沟槽内的多晶硅层上，用于隔离沟槽图案与环境。 密封的外延单晶半导体防止在沟槽图案内形成空隙。 外延层上方的多晶硅层完全覆盖外延半导体生长结构顶部的不期望的尖锐刻面结构。

公开(公告)号：US4924284A

公开(公告)日：1990-05-08

申请号：US145863

申请日：1988-01-20

申请人： Klaus D. Beyer ,  Victor J. Silvestri

发明人： Klaus D. Beyer ,  Victor J. Silvestri

IPC分类号： H01L21/76 ,  H01L21/225 ,  H01L21/74 ,  H01L21/763 ,  H01L29/41

CPC分类号： H01L21/763 ,  H01L21/2255 ,  H01L21/743

摘要： A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

摘要翻译： 在要生产衬底接触的区域和在其他区域中的沟槽隔离的同时产生掺杂的硅填充沟槽的方法。 硼硅酸盐玻璃将需要接触的那些沟槽的侧壁进行配线，并且未掺杂的外延生长的硅填充所有沟槽。 随后的热处理使硼硅酸盐中的硼掺杂在那些沟槽中的外延硅。 在其他沟槽中，除了存在通道停止的底部之外，硅填充物保持未掺杂，从而形成隔离沟槽。 可以通过选择性地将高度掺杂的硅沉积到覆盖在沟槽和相邻衬底表面的一部分的开口中而形成在沟槽上形成的触点。

公开(公告)号：US5392124A

公开(公告)日：1995-02-21

申请号：US169876

申请日：1993-12-17

申请人： Steven G. Barbee ,  Tony F. Heinz ,  Ulrich Hofer ,  Leping Li ,  Victor J. Silvestri

发明人： Steven G. Barbee ,  Tony F. Heinz ,  Ulrich Hofer ,  Leping Li ,  Victor J. Silvestri

IPC分类号： G01B11/06 ,  G01N21/00 ,  G01N21/45 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065

CPC分类号： G01B11/0683

摘要： A method and apparatus for detecting an etching endpoint of a film on a substrate whereby a first excitation beam of light having a prescribed wavelength is provided, the first light beam substantially containing only a first harmonic component of light at that wavelength. The first light beam is directed at a prescribed incident angle to an interface between the film and the substrate, the first light beam being reflected off the interface to thereby provide a second light beam, the second light beam containing the first harmonic component of the first light beam and a generated second harmonic component. The generated second harmonic component is detected and a first output signal representative thereof is provided. A generated second harmonic component reference of the first light beam is produced and a second output signal representative of a generated second harmonic component reference is provided. The detected second harmonic component of the first light beam is normalized, as a function of the first and second output signals, in real-time, and a third output signal representative of an occurrence of a prescribed change in the normalized detected second harmonic component is provided. The prescribed change corresponds to the etching endpoint of the film on the substrate.

摘要翻译： 一种用于检测基板上的膜的蚀刻端点的方法和装置，由此提供具有规定波长的第一激发光束，所述第一光束基本上仅包含该波长的光的一次谐波分量。 第一光束以规定的入射角度指向膜和衬底之间的界面，第一光束从界面反射，从而提供第二光束，第二光束包含第一光束的第一谐波分量 光束和产生的二次谐波分量。 检测所产生的二次谐波分量，并提供代表其的第一输出信号。 产生第一光束的产生的二次谐波分量基准，并且提供表示产生的二次谐波分量基准的第二输出信号。 第一光束的检测到的二次谐波分量被实时地归一化为第一和第二输出信号的函数，并且表示归一化检测的二次谐波分量中的规定变化的发生的第三输出信号是 提供。 规定的变化对应于衬底上的膜的蚀刻终点。

公开(公告)号：US4381818A

公开(公告)日：1983-05-03

申请号：US134243

申请日：1980-03-26

申请人： Kenneth S. Sachar ,  Victor J. Silvestri

发明人： Kenneth S. Sachar ,  Victor J. Silvestri

IPC分类号： C23C14/16 ,  F28F13/18 ,  H01L23/427 ,  H01L23/42

CPC分类号： H01L23/427 ,  C23C14/16 ,  C23C14/165 ,  F28F13/187 ,  H01L2924/0002 ,  Y10S165/907

摘要： A silicon substrate adapted for large scale integrated electronic circuits upon a lower surface has its upper surface coated with a highly porous heat sink film. The film is composed of a porous metal, preferably aluminum, formed by vacuum deposition (evaporation or sputtering) at a high pressure of an inactive gas. The gas can have a pressure of from about 0.5-100 millitorr, and a suitable gas is argon. A porous aluminum film with interconnected nucleation sites which are in the form of reservoir type cavities is manufactured on a silicon surface. The cavities tend to trap vapor of a liquid coolant in contact with the thin film contained in a package enclosing the substrate and its integrated circuit. Cooling fins can be used to cool the coolant.

摘要翻译： 适合于在下表面上的大规模集成电子电路的硅衬底的上表面涂覆有高度多孔的散热片。 该膜由在惰性气体的高压下通过真空沉积（蒸发或溅射）形成的多孔金属，优选铝构成。 气体可以具有约0.5-100毫托的压力，合适的气体是氩气。 在硅表面上制造具有互补成核位置的多孔铝膜，其形式为储层型腔。 空腔倾向于将液体冷却剂的蒸汽与包含在封装衬底及其集成电路的封装中的薄膜接触。 散热片可用于冷却冷却液。