公开(公告)号：US4129801A

公开(公告)日：1978-12-12

申请号：US813240

申请日：1977-07-06

申请人： Ko Soeno ,  Tomio Iizuka ,  Toshio Doi ,  Hisashi Ando ,  Testuo Oyama ,  Hiroshi Sakamoto ,  Akira Misumi

发明人： Ko Soeno ,  Tomio Iizuka ,  Toshio Doi ,  Hisashi Ando ,  Testuo Oyama ,  Hiroshi Sakamoto ,  Akira Misumi

IPC分类号： H01J9/04 ,  H01J29/04 ,  H01J19/06

CPC分类号： H01J29/04 ,  H01J9/04

摘要： The present cathode for cathode ray tube of directly heating type is characterized by comprising a cathode substrate body having two leg pieces extended in the same direction and a flat part connected to one end of each leg piece, prepared by shaping a flat metal plate of nickel- or cobalt-based alloy, a bonding layer having an uneven surface prepared by diffusion bonding by heating a powder layer comprising powders of alloy or mixture of nickel and cobalt formed on the flat part, to which a thermionic emission layer is to be bonded, and the thermionic emission layer, and has a very small deformation when used and a longer life.A cathode with much less deformation and much longer life can be obtained by using a cathode substrate body prepared from a flat metal plate provided with a thinner metal layer of at least one of nickel and cobalt on its surface than the flat metal plate by diffusion bonding.A cathode with much less deformation after the service for a long period and much longer life is obtained by using a cathode substrate body prepared from a flat metal plate provided with a metal layer of at least one of nickel and cobalt having a smaller thickness on its surface than that of the flat metal plate by diffusion bonding, and then applying a plastic working to the flat metal plate to a desired thickness.

摘要翻译： 本发明的直接加热型阴极射线管阴极的特征在于，具有阴极基体，该阴极基体具有沿相同方向延伸的两个腿部件，以及连接到每个腿部件的一端的平坦部件，其通过使镍 或钴基合金，具有通过扩散接合制备的具有不平坦表面的接合层，其通过加热包含在热电子发射层将被结合的平坦部分上形成的合金或镍和钴的混合物的粉末的粉末层， 和热离子发射层，使用时变形非常小，寿命更长。

公开(公告)号：US4114243A

公开(公告)日：1978-09-19

申请号：US775618

申请日：1977-03-08

申请人： Ko Soeno ,  Toshio Doi ,  Tomio Iizuka ,  Hiroshi Sakamoto ,  Hisashi Ando ,  Tetsuo Oyama ,  Akira Misumi

发明人： Ko Soeno ,  Toshio Doi ,  Tomio Iizuka ,  Hiroshi Sakamoto ,  Hisashi Ando ,  Tetsuo Oyama ,  Akira Misumi

IPC分类号： H01J1/14 ,  H01J9/04

CPC分类号： H01J9/04

摘要： In a process for producing a cathode for a cathode ray tube of directly heating type, which comprises shaping a heat-resistant and electro-conductive, flat metal plate, into a cathode substrate body having two leg pieces extended in the same direction and a flat part connected to one end of each leg piece, forming a heat-diffusible metal powder layer having a good affinity to said flat metal plate and on an outer surface of said flat part, heating the powder layer, thereby diffusion bonding the powder layer to the flat part and forming a bonding layer having an uneven surface, to which a thermionic emission layer is to be bonded, and forming the thermionic emission layer on the surface of the bonding layer, the process is characterized by forming on said flat metal plate a metal layer having a good affinity to the flat metal plate, by diffusion bonding, thereby forming a compound plate, and shaping the resulting compound plate into the shape of said cathode substrate body. A cathode having less thermal deformation and a longer life can be produced thereby.Furthermore, the process is characterized by applying a plastic working to the compound plate to a desired thickness and shaping the resulting compound plate into the shape of the cathode substrate body, and a cathode having much less thermal deformation and much longer life can be produced thereby.

摘要翻译： 在直接加热型阴极射线管用阴极的制造方法中，包括将耐热导电平板状金属板成形为具有沿相同方向延伸的两个支腿的阴极基板主体， 形成与所述平板状金属板和所述平坦部的外表面具有良好亲和性的热扩散性金属粉末层，加热所述粉末层，从而将所述粉末层扩散到 并且形成具有不平坦表面的接合层，热电子发射层将被结合到其上，并且在接合层的表面上形成热离子发射层，其特征在于在所述平坦金属板上形成金属 通过扩散接合对平板状金属板具有良好的亲和性，从而形成复合板，并将得到的化合物板成形为所述阴极基体的形状。 因此可以产生具有较少热变形和较长寿命的阴极。

公开(公告)号：US20100003245A1

公开(公告)日：2010-01-07

申请号：US12374473

申请日：2007-07-19

申请人： Toshio Doi ,  Hideharu Abe ,  Naoshi Fukushima ,  Hitoshi Tai ,  Takakazu Mizuno ,  Masahiko Kinosaki

发明人： Toshio Doi ,  Hideharu Abe ,  Naoshi Fukushima ,  Hitoshi Tai ,  Takakazu Mizuno ,  Masahiko Kinosaki

IPC分类号： A61K39/395 ,  C12N5/06 ,  C07K16/18

CPC分类号： C07K16/22 ,  A61K2039/505 ,  C07K2317/76

摘要： When an anti-human BMP antibody was added to cells of an immortalized human mesangial cell line cultured in the presence of human BMP, the anti-human BMP antibody significantly suppressed the production of type IV collagen in mesangial cells. A number of signaling pathways are involved in abnormal proliferation of type IV collagen. It was therefore completely unpredictable whether merely blocking the BMP signal would indeed suppress the abnormal proliferation of type IV collagen. However, for the first time, the present inventors demonstrated that anti-BMP antibodies are very effective in suppressing the abnormal proliferation of type IV collagen. Thus, anti-BMP antibodies can be used as novel therapeutic agents for kidney diseases associated with abnormal proliferation of the mesangial matrix.

摘要翻译： 当将抗人BMP抗体加入到在人BMP存在下培养的永生化人肾小球系膜细胞的细胞中时，抗人BMP抗体显着抑制肾小球系膜细胞中IV型胶原的产生。 许多信号通路涉及IV型胶原异常增殖。 因此，完全不可预测的是，只是阻断BMP信号将确实抑制IV型胶原蛋白的异常增殖。 然而，本发明人第一次证明抗BMP抗体在抑制IV型胶原蛋白的异常增殖方面非常有效。 因此，抗BMP抗体可用作与肾小球系膜基质异常增殖相关的肾脏疾病的新型治疗剂。

公开(公告)号：US5956520A

公开(公告)日：1999-09-21

申请号：US710902

申请日：1996-09-24

申请人： Toshio Kishi ,  Toru Shimizu ,  Shunichi Iwata ,  Shigeo Mizugaki ,  Yuichi Nakao ,  Toshio Doi

发明人： Toshio Kishi ,  Toru Shimizu ,  Shunichi Iwata ,  Shigeo Mizugaki ,  Yuichi Nakao ,  Toshio Doi

IPC分类号： G06F9/30 ,  G06F11/22 ,  G06F11/28 ,  G06F12/08 ,  G06F13/42 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F13/4213

摘要： An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

摘要翻译： 外部总线I / F部分具有这样的功能，其中当由指令执行部分请求总线访问时，由CPU产生的逻辑地址的高位数位从输出端子输出到芯片的外部 作为用于指示由当前执行的程序访问的集成ROM空间，集成RAM空间和外部空间中的哪一个的空间标识符。 使用由CPU生成的地址的一部分，使得当前执行的程序访问的空间从外部实时获知，而不需要外部硬件。

公开(公告)号：US5737589A

公开(公告)日：1998-04-07

申请号：US308346

申请日：1994-09-19

申请人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

发明人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

IPC分类号： G06F13/42 ,  G06F1/12 ,  H04J3/06 ,  H04L7/02 ,  G06F1/06

CPC分类号： H04L7/02

摘要： The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

摘要翻译： 通过根据通过检测采样偏差确定的误差信号的反馈来控制接收机采样时钟和主时钟之间的相位差，相对于用于发起发送的主时钟，连续地调整接收机处的数字信号采样定时 在启动操作和正常操作期间，从期望的基准定时的时钟定时。 通过将采样时钟设置在启动时的所需参考时序来补偿各个器件中的传播延迟散射。 通过在正常工作期间根据接收到的数字信号检测采样时钟定时与参考定时的偏差，然后根据检测结果连续校正采样时钟定时来补偿在器件工作期间引起的传播延迟散射。

公开(公告)号：US5544340A

公开(公告)日：1996-08-06

申请号：US362755

申请日：1994-12-22

申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

IPC分类号： G06F12/08

CPC分类号： G06F12/0886

摘要： A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

摘要翻译： 一种控制设置在CPU和主存储器之间的高速缓冲存储器的方法，其中将要写入高速缓冲存储器的数据和地址对存储在缓冲存储器中。 处理从缓冲存储器读取的多对数据和地址，以比较其地址字段。 基于比较的结果，确定了将数据写入高速缓冲存储器中的写入控制，其被细分为多个存储体。 结果，将多对数据和地址写入高速缓冲存储器的多个组，各对的地址彼此不同。 通过上述规定，可以对高速缓冲存储器的每一组独立地进行写入操作，从而提高写入吞吐量。

公开(公告)号：US5526509A

公开(公告)日：1996-06-11

申请号：US386757

申请日：1995-02-10

申请人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

发明人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0808 ,  G06F12/1063

摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

公开(公告)号：US5065048A

公开(公告)日：1991-11-12

申请号：US397199

申请日：1989-08-23

申请人： Mitsuo Asai ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

发明人： Mitsuo Asai ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

IPC分类号： H03K19/003 ,  H03K19/096

CPC分类号： H03K19/0963 ,  H03K19/00338

摘要： A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.

摘要翻译： 一种动态半导体逻辑电路，包括：MOS FET逻辑部分，用于响应输入模式预充电之后的输入逻辑信号和所述逻辑部分的内部节点进行高速逻辑运算; CMOS / BiCMOS输出缓冲器部分，用于输出 逻辑运算，以及噪声抑制部，用于防止误操作而不牺牲高速运行特性。 该电路采用0.5μm规则技术制造，并且在4.5 V或更低的低压电源下以高速运行，具有预充电部分，用于对MOS FET逻辑部分的输出节点和内部节点进行预充电 以及噪声抑制部分，用于通过反馈输出缓冲器部分的输出来将逻辑部分的输出节点锁存到源极电位，以便放大软误差容限。 闭锁电流保持在小于预定比率以保持高速操作特性。

公开(公告)号：US20160333412A1

公开(公告)日：2016-11-17

申请号：US15146515

申请日：2016-05-04

申请人： Toshio Doi ,  HUBIT GENOMIX INC.

发明人： Toshio Doi ,  Hideharu ABE

IPC分类号： C12Q1/68 ,  C07K16/28 ,  G01N33/68

CPC分类号： C12Q1/6883 ,  A61K45/06 ,  C07K16/2863 ,  C07K2317/76 ,  C12Q2600/106 ,  C12Q2600/158 ,  G01N33/6893 ,  G01N2333/4703 ,  G01N2333/4706 ,  G01N2333/51 ,  G01N2333/71

摘要： A method of detecting proliferative diseases causing sclerosis, comprising measuring the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1, phosphorylated Smad1, activin receptor-like kinase 1, activin receptor-like kinase 3 and bone morphogenetic proteins in a biological sample. A kit therefor. A prophylactic and/or therapeutic agent for proliferative diseases causing sclerosis, comprising as an active ingredient a substance having an inhibitory effect on the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A method of identifying substances effective in preventing and/or treating proliferative diseases causing sclerosis, comprising judging whether or not a test substance inhibits the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A kit therefor.

摘要翻译： 一种检测引起硬化的增殖性疾病的方法，包括测量选自STAT3，磷酸化STAT3，Smad1，磷酸化Smad1，激活素受体样激酶1，激活素受体样激酶3和骨形态发生的至少一种物质的表达 生物样品中的蛋白质。 一个套件。 一种引起硬化的增殖性疾病的预防和/或治疗剂，其包含作为活性成分的对STAT3，磷酸化STAT3，Smad1和磷酸化Smad1中选择的至少一种物质的表达具有抑制作用的物质。 鉴定有效预防和/或治疗引起硬化的增殖性疾病的物质的方法，包括判断测试物质是否抑制至少一种选自STAT3，磷酸化STAT3，Smad1和磷酸化Smad1的物质的表达。 一个套件。

公开(公告)号：US20100135988A1

公开(公告)日：2010-06-03

申请号：US12585882

申请日：2009-09-28

申请人： Toshio Doi ,  Hideharu Abe

发明人： Toshio Doi ,  Hideharu Abe

IPC分类号： A61K39/395 ,  C12Q1/00 ,  C12Q1/68 ,  G01N33/53 ,  C12Q1/48 ,  G01N33/561 ,  A61K31/7088

CPC分类号： C12Q1/6883 ,  A61K45/06 ,  C07K16/2863 ,  C07K2317/76 ,  C12Q2600/106 ,  C12Q2600/158 ,  G01N33/6893 ,  G01N2333/4703 ,  G01N2333/4706 ,  G01N2333/51 ,  G01N2333/71

摘要： A method of detecting proliferative diseases causing sclerosis, comprising measuring the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1, phosphorylated Smad1, activin receptor-like kinase 1, activin receptor-like kinase 3 and bone morphogenetic proteins in a biological sample. A kit therefor. A prophylactic and/or therapeutic agent for proliferative diseases causing sclerosis, comprising as an active ingredient a substance having an inhibitory effect on the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A method of identifying substances effective in preventing and/or treating proliferative diseases causing sclerosis, comprising judging whether or not a test substance inhibits the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A kit therefor.

摘要翻译： 一种检测引起硬化的增殖性疾病的方法，包括测量选自STAT3，磷酸化STAT3，Smad1，磷酸化Smad1，激活素受体样激酶1，激活素受体样激酶3和骨形态发生的至少一种物质的表达 生物样品中的蛋白质。 一个套件。 一种引起硬化的增殖性疾病的预防和/或治疗剂，其包含作为活性成分的对STAT3，磷酸化STAT3，Smad1和磷酸化Smad1中选择的至少一种物质的表达具有抑制作用的物质。 鉴定有效预防和/或治疗引起硬化的增殖性疾病的物质的方法，包括判断测试物质是否抑制至少一种选自STAT3，磷酸化STAT3，Smad1和磷酸化Smad1的物质的表达。 一个套件。