公开(公告)号：US08685267B2

公开(公告)日：2014-04-01

申请号：US13165951

申请日：2011-06-22

申请人： Koichi Yatsuda ,  Hiromasa Mochiki

发明人： Koichi Yatsuda ,  Hiromasa Mochiki

IPC分类号： B44C1/22

CPC分类号： H01L21/6719 ,  H01J37/32091 ,  H01J37/32146 ,  H01J37/32165 ,  H01L21/3065

摘要： There is provided a substrate processing method capable of preventing the decrease in etching efficiency by positive ions and increasing the overall etching efficiency by using negative ions. The substrate processing method includes applying a plasma RF and a bias RF in the pattern of a pulse wave, respectively. The substrate processing method repeatedly performs the steps of: (3b) etching a substrate by positive ions in plasma by applying both the plasma RF and the bias RF; (3c) generating negative ions in a processing chamber by stopping the application of both the plasma RF and the bias RF; and (3a) attracting the negative ions to the substrate by applying the bias RF and stopping the application of the plasma RF. A duty ratio of the bias RF is set to be greater than a duty ratio of the plasma RF.

摘要翻译： 提供了一种能够防止正离子蚀刻效率降低并且通过使用负离子提高整体蚀刻效率的衬底处理方法。 基板处理方法包括分别在脉波图案中施加等离子体RF和偏压RF。 基板处理方法重复执行以下步骤：（3b）通过施加等离子体RF和偏压RF两者来蚀刻等离子体中的正离子; （3c）通过停止施加等离子体RF和偏压RF来在处理室中产生负离子; 和（3a）通过施加偏压RF并停止施加等离子体RF来吸引负离子到衬底。 偏置RF的占空比被设定为大于等离子体RF的占空比。

公开(公告)号：US08641916B2

公开(公告)日：2014-02-04

申请号：US12692913

申请日：2010-01-25

申请人： Koichi Yatsuda ,  Yoshinobu Ooya ,  Shin Okamoto ,  Hiromasa Mochiki

发明人： Koichi Yatsuda ,  Yoshinobu Ooya ,  Shin Okamoto ,  Hiromasa Mochiki

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01J37/32146 ,  H01J37/32091 ,  H01J37/32697

摘要： A plasma etching method for forming a hole in an etching target film by a plasma processing apparatus is provided. The apparatus includes an RF power supply for applying RF power for plasma generation to at least one of upper and lower electrodes, and a DC power supply for applying minus DC voltage to the upper electrode. A first condition that plasma is generated by turning on the RF power supply and minus DC voltage is applied to the upper electrode and a second condition that the plasma is extinguished by turning off the RF power supply and minus DC voltage is applied to the upper electrode are alternately repeated. Etching is performed by positive ions in the plasma under the first condition and negative ions are supplied into the hole by the DC voltage to neutralize positive ions in the hole under the second condition.

摘要翻译： 提供了一种通过等离子体处理装置在蚀刻靶膜中形成孔的等离子体蚀刻方法。 该装置包括用于向上电极和下电极中的至少一个施加用于等离子体产生的RF功率的RF电源，以及用于向上电极施加负DC电压的DC电源。 通过接通RF电源产生等离子体的第一条件和负DC电压被施加到上电极，并且通过关闭RF电源而将等离子体熄灭的第二条件并且将负DC电压施加到上电极 交替重复。 在第一条件下，通过正离子在等离子体中进行蚀刻，并且通过DC电压将负离子供给到孔中，以在第二条件下中和孔中的正离子。

公开(公告)号：US20110318933A1

公开(公告)日：2011-12-29

申请号：US13165951

申请日：2011-06-22

申请人： Koichi Yatsuda ,  Hiromasa Mochiki

发明人： Koichi Yatsuda ,  Hiromasa Mochiki

IPC分类号： H01L21/3065

CPC分类号： H01L21/6719 ,  H01J37/32091 ,  H01J37/32146 ,  H01J37/32165 ,  H01L21/3065

摘要： There is provided a substrate processing method capable of preventing the decrease in etching efficiency by positive ions and increasing the overall etching efficiency by using negative ions. The substrate processing method includes applying a plasma RF and a bias RF in the pattern of a pulse wave, respectively. The substrate processing method repeatedly performs the steps of: (3b) etching a substrate by positive ions in plasma by applying both the plasma RF and the bias RF; (3c) generating negative ions in a processing chamber by stopping the application of both the plasma RF and the bias RF; and (3a) attracting the negative ions to the substrate by applying the bias RF and stopping the application of the plasma RF. A duty ratio of the bias RF is set to be greater than a duty ratio of the plasma RF.

摘要翻译： 提供了一种能够防止正离子蚀刻效率降低并且通过使用负离子提高整体蚀刻效率的衬底处理方法。 基板处理方法包括分别在脉波图案中施加等离子体RF和偏压RF。 基板处理方法重复执行以下步骤：（3b）通过施加等离子体RF和偏压RF两者来蚀刻等离子体中的正离子; （3c）通过停止施加等离子体RF和偏压RF来在处理室中产生负离子; 和（3a）通过施加偏压RF并停止施加等离子体RF来吸引负离子到衬底。 偏置RF的占空比被设定为大于等离子体RF的占空比。

公开(公告)号：US07871908B2

公开(公告)日：2011-01-18

申请号：US12407854

申请日：2009-03-20

申请人： Koichi Yatsuda ,  Eiichi Nishimura

发明人： Koichi Yatsuda ,  Eiichi Nishimura

IPC分类号： H01L21/425

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31138 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  Y10S438/948 ,  Y10S438/975

摘要： The method of manufacturing a semiconductor device comprising: forming a first hard mask layer and a second hard mask layer on the layer to be etched (S11); a first groove-forming mask pattern forming process for forming a groove-forming mask pattern which has a first pitch, is formed of the second hard mask layer, and is used as an etching mask when forming groove patterns(S12-S14); and a first concave portion-forming mask pattern forming process for etching the first hard mask layer using the second resist pattern as an etching mask, wherein the second resist pattern is formed of the second resist layer having an opening portion that has a fourth pitch and the first organic layer having an opening portion that is connected to an opening portion of the second resist layer and has a smaller size than the opening portion of the second resist layer (S15-S18).

摘要翻译： 制造半导体器件的方法包括：在被蚀刻层上形成第一硬掩模层和第二硬掩模层（S11）; 用于形成具有第一间距的沟槽形成掩模图案的第一凹槽形成掩模图案形成工艺由第二硬掩模层形成，并且在形成凹槽图案时用作蚀刻掩模（S12-S14）。 以及使用第二抗蚀剂图案作为蚀刻掩模来蚀刻第一硬掩模层的第一凹部形成掩模图案形成工艺，其中第二抗蚀剂图案由具有第四间距的开口部分的第二抗蚀剂层形成，以及 所述第一有机层具有与所述第二抗蚀剂层的开口部连接并且具有比所述第二抗蚀剂层的开口部小的尺寸的开口部（S15-S18）。

公开(公告)号：US20090087991A1

公开(公告)日：2009-04-02

申请号：US12284750

申请日：2008-09-24

申请人： Koichi Yatsuda ,  Eiichi Nishimura

发明人： Koichi Yatsuda ,  Eiichi Nishimura

IPC分类号： H01L21/3105

CPC分类号： H01L21/32139 ,  H01L21/0337

摘要： A manufacturing method of a semiconductor device, which etches a layer to be etched on a substrate into a predetermined pattern based on a first pattern of photoresist produced by exposing and developing a photoresist film, the manufacturing method includes the steps of, patterning an organic membrane based on a first pattern of the photoresist, forming an SiO2 film on the patterned organic membrane, etching the SiO2 film so that the SiO2 remains only in a side wall section of the organic membrane and forming a second pattern of the SiO2 film by removing the organic membrane.

摘要翻译： 一种半导体器件的制造方法，其基于通过曝光和显影光致抗蚀剂膜产生的光致抗蚀剂的第一图案将基板上待刻蚀的层蚀刻成预定图案，所述制造方法包括以下步骤：将有机膜图案化 基于光致抗蚀剂的第一图案，在图案化有机膜上形成SiO 2膜，蚀刻SiO 2膜，使得SiO 2仅保留在有机膜的侧壁部分中，并通过除去SiO 2膜形成第二图案 有机膜。

公开(公告)号：US6156151A

公开(公告)日：2000-12-05

申请号：US895993

申请日：1997-07-17

申请人： Mitsuaki Komino ,  Junichi Arami ,  Koichi Yatsuda

发明人： Mitsuaki Komino ,  Junichi Arami ,  Koichi Yatsuda

IPC分类号： H01J37/32 ,  C23F1/02 ,  C23C16/00

CPC分类号： H01J37/3244 ,  H01J37/32458 ,  H01J37/32834

摘要： A plasma etching apparatus has a central processing chamber, an upper exhaust chamber thereabove, and a lower exhaust chamber therebelow. The processing chamber, the upper exhaust chamber, and the lower exhaust chamber are airtightly formed by a central casing part, an upper casing part, and a lower casing part which are separably combined. The upper and lower exhaust chambers are respectively connected to upper and lower exhaust pumps. A susceptor having a support surface for supporting a target object, and an upper electrode or shower head opposing it are arranged in the processing chamber. A processing gas spouted through the shower head flows upward and downward toward the upper and lower exhaust chambers via the processing chamber.

摘要翻译： 等离子体蚀刻装置具有中央处理室，上部排气室和下部排气室。 处理室，上排气室和下排气室由可分离组合的中央壳体部分，上壳体部分和下壳体部分气密地形成。 上排气室和下排气室分别连接到上排气泵和下排气泵。 具有用于支撑目标物体的支撑表面的基座和与其对置的上部电极或淋浴喷头布置在处理室中。 通过喷淋头喷出的处理气体经由处理室向上下排气室上下流动。

公开(公告)号：US20100300622A1

公开(公告)日：2010-12-02

申请号：US12788396

申请日：2010-05-27

申请人： Koichi Yatsuda ,  Hideki Mizuno

发明人： Koichi Yatsuda ,  Hideki Mizuno

IPC分类号： C23F1/08

CPC分类号： H01J37/32642 ,  H01J37/32091

摘要： A plasma processing apparatus includes a processing chamber the inside of which is maintained in a vacuum; a mounting table configured to mount a target substrate and serve as a lower electrode in the processing chamber; a circular ring-shaped member provided at the mounting table so as to surround a peripheral portion of the target substrate; an upper electrode arranged to face the lower electrode thereabove; and a power feed unit for supplying a high frequency power to the mounting table. The apparatus performs a plasma process on the target substrate by plasma generated in the processing chamber. The circular ring-shaped member includes at least one ring-shaped groove configured to adjust an electric field distribution to a desired distribution in a plasma generation space, and the groove is formed in a surface of the circular ring-shaped member and the surface is on an opposite side to the plasma generation space.

摘要翻译： 等离子体处理装置包括处理室，其内部保持在真空中; 安装台，被配置为安装目标基板并用作处理室中的下电极; 设置在所述安装台上以围绕所述目标基板的周边部分的圆形环状部件; 上电极，其布置成面向其上方的下电极; 以及用于向安装台提供高频电力的供电单元。 该装置通过处理室中产生的等离子体对目标衬底进行等离子体处理。 圆形环状构件包括至少一个环形槽，其构造成将等离子体产生空间中的电场分布调节到期望的分布，并且所述凹槽形成在圆形环形构件的表面中，并且表面是 在等离子体产生空间的相对侧。

公开(公告)号：US20050103441A1

公开(公告)日：2005-05-19

申请号：US10844498

申请日：2004-05-13

申请人： Masanobu Honda ,  Kazuya Nagaseki ,  Hanako Kida ,  Koichi Yatsuda ,  Youbun Ito ,  Koichiro Inazawa ,  Rie Inazawa ,  Hisataka Hayashi

发明人： Masanobu Honda ,  Kazuya Nagaseki ,  Hanako Kida ,  Koichi Yatsuda ,  Youbun Ito ,  Koichiro Inazawa ,  Rie Inazawa ,  Hisataka Hayashi

IPC分类号： H01L21/311 ,  H01L21/306

CPC分类号： H01J37/32082 ,  H01J37/32706 ,  H01L21/31116 ,  H01L21/31144

摘要： There is provided an etching method and a plasma etching apparatus capable of taking a large etching selection ratio and of forming a hole having an appropriate shape. When etching an etching target film 204 by using an organic film 202 having a predetermined pattern as a mask, processing gas is introduced into an airtight processing container 104. There are provided a high frequency power source 122 of 40 MHz and a high frequency power source 128 of 3.2 MHz, by which two different kinds of high frequency powers are applied to a lower electrode 106. The power of each high frequency power is properly combined, thereby executing the etching process by using low plasma electron density Ne and high self-bias voltage Vdc which are generated by high frequency power.

摘要翻译： 提供了能够获得大的蚀刻选择比和形成具有适当形状的孔的蚀刻方法和等离子体蚀刻装置。 当通过使用具有预定图案的有机膜202作为掩模蚀刻蚀刻目标膜204时，处理气体被引入到气密处理容器104中。 提供40MHz的高频电源122和3.2MHz的高频电源128，通过该高频电源128将两种不同种类的高频功率施加到下电极106。 每个高频功率的功率被适当组合，从而通过使用由高频功率产生的低等离子体电子密度Ne和高自偏压Vdc来执行蚀刻处理。

公开(公告)号：US06488863B2

公开(公告)日：2002-12-03

申请号：US09970852

申请日：2001-10-05

申请人： Koichi Yatsuda ,  Tetsuya Nishiara ,  Kouichiro Inazawa ,  Shin Okamoto

发明人： Koichi Yatsuda ,  Tetsuya Nishiara ,  Kouichiro Inazawa ,  Shin Okamoto

IPC分类号： H01L213065

CPC分类号： H01L21/31116

摘要： An etching gas is supplied into a process chamber and turned into plasma so as to etch a silicon nitride film arranged on a field silicon oxide film on a wafer (w). A mixture gas containing at least CH2F2 gas and O2 gas is used as the etching gas. Parameters for planar uniformity, by which the etching apparatus is set in light of a set value of the planar uniformity, include the process pressure and the mixture ratio (CH2F2/O2) of the mixture gas. As the set value of the planar uniformity is more strict, either one of the process pressure and the mixture ratio is set higher.

公开(公告)号：US08198183B2

公开(公告)日：2012-06-12

申请号：US12441823

申请日：2008-10-23

申请人： Koichi Yatsuda ,  Eiichi Nishimura

发明人： Koichi Yatsuda ,  Eiichi Nishimura

IPC分类号： H01L21/38 ,  H01L21/4763

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A feedforward control is performed so that a line width of a mask constituted by an Si3N4 layer 102 formed by using a photoresist 105b as a mask is to be the same as a line width of a mask pattern constituted by an SiO2 layer 103 based on a measured line width of the photoresist 105b and the measured line width of the mask pattern constituted by the SiO2 layer 103. For example, a control of a trimming amount of the line width of the photoresist 105b is performed so that the line width of the photoresist 105b is to be the same as the line width of the mask pattern constituted by the SiO2 layer 103.

摘要翻译： 执行前馈控制，使得由通过使用光致抗蚀剂105b作为掩模形成的由Si 3 N 4层102构成的掩模的线宽度将与由基于SiO 2的SiO 2层103构成的掩模图案的线宽相同 测量光致抗蚀剂105b的线宽以及由SiO 2层103构成的掩模图案的测量线宽。例如，对光致抗蚀剂105b的线宽进行修整量的控制，使得光致抗蚀剂的线宽 105b与由SiO 2层103构成的掩模图案的线宽相同。