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    Semiconductor memory device having flip-flop circuits
    1.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US5132771A

    公开(公告)日：1992-07-21

    申请号：US503928

    申请日：1990-04-04

    申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    IPC分类号： G11C11/412 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

    摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

    Constant current-constant voltage circuit
    3.
    发明授权
    Constant current-constant voltage circuit 失效
    恒流恒压电路

    公开(公告)号：US5047706A

    公开(公告)日：1991-09-10

    申请号：US577512

    申请日：1990-09-05

    申请人： Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi

    发明人： Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi

    IPC分类号： G05F1/46 ,  G05F3/24 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04

    CPC分类号： G05F3/247 ,  G05F1/463 ,  G05F1/465 ,  G05F3/245 ,  Y10S323/907

    摘要： In a constant current-constant voltage circuit disclosed herein, gates of MOSFETs Q.sub.1 and Q.sub.2 are connected together, and the gate of the MOSFET Q.sub.1 is connected to the drain thereof. Further, the source of the MOSFET Q.sub.1 is connected to ground potential GND whereas the source of the MOSFET Q.sub.2 is connected to the drain of a MOSFET Q.sub.3 having a gate connected to power supply voltage V.sub.DD and a source connected to the ground voltage GND. A current mirror circuit including Q.sub.4 and Q.sub.5 has an input and an output respectively connected to the drain of the second MOSFET Q.sub.2 and the drain of the first MOSFET Q.sub.1. A first coefficient (W.sub.3 L.sub.2 /L.sub.3 W.sub.2) depending upon channel lengths (L.sub.2, L.sub.3) and channel widths (W.sub.2, W.sub.3) of the MOSFETs Q.sub.2 and Q.sub.3 is set at a value not larger than a predetermined value. Therefore, the MOSFET Q.sub.3 operates in a linear region as high resistance, and the MOSFETs Q.sub.1 and Q.sub.2 operate in a sub-threshold region. As a result, the dependence upon temperature is significantly improved.

    摘要翻译： 在本文公开的恒定电流恒定电压电路中，MOSFET Q1和Q2的栅极连接在一起，并且MOSFET Q1的栅极连接到其漏极。 此外，MOSFET Q1的源极连接到地电位GND，而MOSFET Q2的源极连接到具有连接到电源电压VDD的栅极和连接到地电压GND的源极的MOSFET Q3的漏极。 包括Q4和Q5的电流镜电路具有分别连接到第二MOSFET Q2的漏极和第一MOSFET Q1的漏极的输入和输出。 取决于MOSFET Q2和Q3的沟道长度（L2，L3）和沟道宽度（W2，W3）的第一系数（W3L2 / L3W2）被设置为不大于预定值的值。 因此，MOSFET Q3以高电阻工作在线性区域，并且MOSFET Q1和Q2在亚阈值区域中工作。 结果，对温度的依赖性显着提高。

    Sense amplifier for a memory device
    4.
    发明授权
    Sense amplifier for a memory device 失效
    用于存储器件的感应放大器

    公开(公告)号：US5126974A

    公开(公告)日：1992-06-30

    申请号：US465040

    申请日：1990-01-16

    申请人： Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Koichiro Ishibashi ,  Shoji Hanamura

    发明人： Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Koichiro Ishibashi ,  Shoji Hanamura

    IPC分类号： G11C7/06 ,  G11C11/419

    CPC分类号： G11C7/062 ,  G11C11/419 ,  G11C7/065

    摘要： A MOS transistor sense amplifier employs cross coupled positive feedback for the load circuit of a differential amplifier with an equalizing switch at the amplifier output, and preferably also at the input. This basis amplifier circuit may be repeated in stages. When stages are employed, it is desirable that the first stage employs current mirror loading of the differential amplifier to reduce the data delay. Data delay is further reduced by providing strong amplification during the sense portion of the read cycle with a preamplifier, which preamplifier has its amplification reduced, preferably to unity by being turned off, when the sense portion of the cycle is finished, and most preferably when the input and output data lines are directly connected independently of the preamplifier, so that the preamplifier may be completely turned off to lower power consumption.

    摘要翻译： MOS晶体管感测放大器采用交叉耦合的正反馈给差分放大器的负载电路，在放大器输出端具有均衡开关，优选也在输入端。 该基本放大器电路可以分阶段地重复。 当采用级时，期望第一级采用差分放大器的电流镜像负载来减少数据延迟。 通过在读周期的感测部分期间通过在前置放大器上提供强放大来进一步降低数据延迟，当循环的感测部分完成时，前置放大器的放大减小，优选地被关闭，优选地，当 输入和输出数据线独立于前置放大器直接连接，从而可以完全关闭前置放大器以降低功耗。

    Semiconductor memory having redundancy circuit for relieving defects
    5.
    发明授权
    Semiconductor memory having redundancy circuit for relieving defects 失效
    具有用于消除缺陷的冗余电路的半导体存储器

    公开(公告)号：US5021944A

    公开(公告)日：1991-06-04

    申请号：US376245

    申请日：1989-07-06

    申请人： Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Shoji Hanamura

    发明人： Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Shoji Hanamura

    IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/846

    摘要： A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare memory array. A first word from the first memory array is selected concurrently with a first substitute word from the first spare memory. An address signal is decoded and then compared with data representative of a defective word. In the event it is determined, as a result of this comparison, that the first word is defective, the first substitute word is then communicated to a common data bus. Alternatively, the first word is communicated to the common data bus.

    摘要翻译： 用替代存储器元件快速掩蔽有缺陷的存储器元件的方法和装置包括第一和第二存储器块。 第一存储器块包括第一存储器阵列和第二备用存储器阵列。 第二存储器块包括第二存储器阵列和第一备用存储器阵列。 与来自第一备用存储器的第一替代字同时选择来自第一存储器阵列的第一个字。 地址信号被解码，然后与表示有缺陷的字的数据进行比较。 在确定的情况下，作为该比较的结果，第一个字是有缺陷的，然后第一个替代字被传送到公共数据总线。 或者，第一个字被传送到公共数据总线。

    Logic circuit and data processing apparatus using the same
    6.
    发明授权
    Logic circuit and data processing apparatus using the same 失效
    逻辑电路及使用其的数据处理装置

    公开(公告)号：US5148387A

    公开(公告)日：1992-09-15

    申请号：US480674

    申请日：1990-02-15

    申请人： Kazuo Yano ,  Koichiro Ishibashi ,  Tetsuya Nakagawa ,  Katsuhiro Shimohigashi ,  Osamu Minato

    发明人： Kazuo Yano ,  Koichiro Ishibashi ,  Tetsuya Nakagawa ,  Katsuhiro Shimohigashi ,  Osamu Minato

    IPC分类号： G06F7/50 ,  G06F7/501

    CPC分类号： G06F7/5016

    摘要： A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.

    摘要翻译： 逻辑电路包括第一，第二，第三，第四，第五和第六场效应晶​​体管或FET，输入节点和输出节点。 第五和第六FET连接到输出节点。 第一和第三FET连接到第五FET。 第二和第四FET连接到第六FET。 第一和第二FET连接到第一输入节点。 第三和第四FET连接到第二节点。 第一信号被提供给第一输入节点。 向第一和第四FET的栅电极提供第二信号。 具有与第二信号相反的相位的信号被提供给第二和第三FET的栅电极。 第三信号被提供给第二输入节点。 从第一，第二和第三信号中选择的一个信号被提供给第五FET的栅电极。 具有与提供给第五FET的栅电极的信号相反的相位的信号被提供给第六FET的栅电极。 从输出节点生成与第一，第二和第三输入信号有关的输出信号。 输出信号例如是进位输出信号或多数决定逻辑输出信号。

    High speed MOSFET output buffer with low noise
    7.
    发明授权
    High speed MOSFET output buffer with low noise 失效
    高速MOSFET输出缓冲器，噪音低

    公开(公告)号：US4992677A

    公开(公告)日：1991-02-12

    申请号：US325439

    申请日：1989-03-20

    申请人： Koichiro Ishibashi ,  Osamu Minato ,  Katsuhiro Shimohigashi

    发明人： Koichiro Ishibashi ,  Osamu Minato ,  Katsuhiro Shimohigashi

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K17/166 ,  H03K19/00361

    摘要： A semiconductor integrated circuit includes: a data output terminal; a first semiconductor element connected between a first operating potential point and the data output terminal; a second semiconductor element connected between the data output terminal and a second operating potential point; first control means connected to a control input terminal of the first semiconductor element; second control means connected to a control input terminal of the second semiconductor element; first generating means for generating a first predetermined voltage; and second generating means for generating a second predetermined voltage higher than the first predetermined voltage. When voltage at the data output terminal is higher than the second predetermined voltage, the first control means controls the first semiconductor element to be in the OFF-state, and the second control means controls the second semiconductor element to be in the ON-state to lower the voltage of the data output terminal to the second predetermined voltage. On the other hand, in the case where the voltage of the data output terminal is lower than that of the first predetermined voltage, the output of the first control means controls the first semiconductor element so that it is in the ON-state and the output of the second control means controls the second semiconductor element so that it is in the OFF-state so as to raise the voltage of the data output terminal to the first predetermined voltage.

    摘要翻译： 半导体集成电路包括：数据输出端子; 连接在第一操作电位点和数据输出端之间的第一半导体元件; 连接在数据输出端和第二工作电位之间的第二半导体元件; 连接到第一半导体元件的控制输入端的第一控制装置; 连接到第二半导体元件的控制输入端子的第二控制装置; 用于产生第一预定电压的第一产生装置; 以及第二产生装置，用于产生高于第一预定电压的第二预定电压。 当数据输出端子的电压高于第二预定电压时，第一控制装置控制第一半导体元件处于截止状态，第二控制装置将第二半导体元件控制在导通状态 将数据输出端子的电压降低到第二预定电压。 另一方面，在数据输出端子的电压低于第一预定电压的电压的情况下，第一控制装置的输出控制第一半导体元件使其处于导通状态并且输出 所述第二控制装置控制所述第二半导体元件使其处于截止状态，以将所述数据输出端子的电压升高到所述第一预定电压。