公开(公告)号：US09240511B2

公开(公告)日：2016-01-19

申请号：US14143176

申请日：2013-12-30

Applicant: Korea Institute of Science and Technology

Inventor： Seung Yong Lee ,  Jin Dong Song ,  So-Hye Cho ,  Jin Ock Park ,  Jong-Ku Park

IPC: H01L31/02 ,  H01L31/112 ,  H01L31/0224 ,  H01L31/0232 ,  H01L31/09

CPC classification number: H01L31/1126 ,  H01L31/0224 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/09

Abstract: Disclosed is a photodetector including an electrically conductive substrate, a first electrode formed on the substrate, a second electrode disposed to be spaced apart from the first electrode, a plasmonic nanostructure positioned between the first electrode and the second electrode and having surface plasmon resonance, and a resistance measuring device or an electrical conductivity measuring device connected to the first electrode and the second electrode.

Abstract translation: 公开了一种光电检测器，其包括导电基板，形成在基板上的第一电极，设置成与第一电极间隔开的第二电极，位于第一电极和第二电极之间并具有表面等离子体共振的等离子体纳米结构，以及 连接到第一电极和第二电极的电阻测量装置或电导率测量装置。

公开(公告)号：US09331266B2

公开(公告)日：2016-05-03

申请号：US14132492

申请日：2013-12-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY ,  THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF THE NAVY

Inventor： Joon Yeon Chang ,  Jin Ki Hong ,  Jin Dong Song ,  Mark Johnson

IPC: H03K19/173 ,  H01L43/02 ,  H01L27/22 ,  H03K19/0175 ,  H03K19/16 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1695 ,  H01L27/22 ,  H01L43/08 ,  H03K19/017581 ,  H03K19/16

Abstract: A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer.

Abstract translation: 提供执行逻辑操作和存储功能并由磁场控制的非易失性可重构逻辑器件。 该可重构逻辑器件包括i）至少一个半导体器件; 以及ii）一对磁场控制装置，其分别与所述半导体器件的两侧间隔开并且适于产生磁场泄漏以控制所述半导体器件。 半导体器件包括i）第一半导体层; 以及ii）位于所述第一半导体层上的第二半导体层。 第一半导体层和第二半导体层中的一个是p型半导体层，另一个是n型半导体层。

公开(公告)号：US08895412B2

公开(公告)日：2014-11-25

申请号：US13668526

申请日：2012-11-05

Applicant: Korea Institute of Science and Technology

Inventor： Seung Kyu Ha ,  Su Youn Kim ,  Il Ki Han ,  Jin Dong Song ,  Won Jun Choi

IPC: H01L21/20 ,  H01L21/02 ,  H01L29/12 ,  B82Y10/00 ,  H01L29/06 ,  G01N21/00 ,  H01L29/76 ,  B82Y40/00

CPC classification number: H01L21/02104 ,  B82Y10/00 ,  B82Y40/00 ,  G01N21/00 ,  H01L21/02546 ,  H01L21/02601 ,  H01L21/02631 ,  H01L29/0665 ,  H01L29/127 ,  H01L29/7613 ,  Y10S977/84

Abstract: Disclosed is a nano-structure manufacturing method which includes: forming a first semiconductor composite layer, a semiconductor quantum structure layer, a second semiconductor composite layer, and a semiconductor quantum dot layer on a substrate in order; thermally treating the semiconductor quantum dot layer so that quantum dots of the semiconductor quantum dot layer are aggregated; and performing an etching process by using the aggregated quantum dots as a mask.

Abstract translation: 公开了一种纳米结构制造方法，其包括：依次在基板上形成第一半导体复合层，半导体量子结构层，第二半导体复合层和半导体量子点层; 热处理半导体量子点层，使半导体量子点层的量子点聚集; 并且通过使用聚合的量子点作为掩模来执行蚀刻处理。