公开(公告)号：US5109492A

公开(公告)日：1992-04-28

申请号：US84808

申请日：1987-08-13

申请人： Kouki Noguchi ,  Yoshimune Hagiwara ,  Kazuhiko Iwasaki ,  Hirokazu Aoki ,  Shigeru Shimada

发明人： Kouki Noguchi ,  Yoshimune Hagiwara ,  Kazuhiko Iwasaki ,  Hirokazu Aoki ,  Shigeru Shimada

IPC分类号： G06F13/36 ,  G06F13/42

CPC分类号： G06F13/4208 ,  G06F13/36

摘要： A microprocessor suitable for a high speed processor system prevents extension of a bus cycle due to delay of generation of a bus cycle end signal and effectively utilizes a characteristic of a high speed accessable external device.

摘要翻译： 适用于高速处理器系统的微处理器防止由于总线周期结束信号的产生的延迟而导致总线周期的扩展，并且有效地利用高速可访问的外部设备的特性。

公开(公告)号：US4812969A

公开(公告)日：1989-03-14

申请号：US865840

申请日：1986-05-22

申请人： Katsuaki Takagi ,  Hirokazu Aoki ,  Norio Nakagawa ,  Yoshimune Hagiwara

发明人： Katsuaki Takagi ,  Hirokazu Aoki ,  Norio Nakagawa ,  Yoshimune Hagiwara

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F9/32 ,  G06F9/36

CPC分类号： G06F12/1036

摘要： An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative memory array which stores and compares addresses. The associative memory array is provided with a circuit which, when a specific value is set in a common area field, invalidates comparison in a space number field.

摘要翻译： 在具有多虚拟空间的计算机系统中使用的地址转换单元包括全关联翻译后备缓冲器（TLB），其对于每个条目包括存储和比较地址的关联存储器阵列。 关联存储器阵列设置有当在公共区域字段中设置特定值时使空格号字段中的比较无效的电路。

公开(公告)号：US5193075A

公开(公告)日：1993-03-09

申请号：US490745

申请日：1990-03-08

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US5146573A

公开(公告)日：1992-09-08

申请号：US426781

申请日：1989-10-25

申请人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G06F12/0804

摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US4519049A

公开(公告)日：1985-05-21

申请号：US446510

申请日：1982-12-03

申请人： Takashi Toyooka ,  Hirokazu Aoki ,  Mamoru Sugie

发明人： Takashi Toyooka ,  Hirokazu Aoki ,  Mamoru Sugie

IPC分类号： G11C11/14 ,  G11C19/08

CPC分类号： G11C19/0875

摘要： A magnetic bubble memory has a plurality of minor loops for storing data represented by magnetic bubble sequences, a write line for transferring write data to couple them to the minor loops and a read line for transferring read data to a bubble detector. The read line is coupled to a plurality of auxiliary loops through replicators and the auxiliary loops are coupled to the minor loops through replicators. The data replicated to the auxiliary loops are read out.

摘要翻译： 磁气泡存储器具有多个次循环，用于存储由磁气泡序列表示的数据，用于传送写数据以将其耦合到次循环的写入线和用于将读取数据传送到气泡检测器的读取线。 读线路通过复制器耦合到多个辅助回路，并且辅助回路通过复制器耦合到次循环。 读出复制到辅助回路的数据。

公开(公告)号：US4247911A

公开(公告)日：1981-01-27

申请号：US29056

申请日：1979-04-11

申请人： Shigeru Yoshizawa ,  Hirokazu Aoki ,  Shinsaku Chiba ,  Koichi Mayama ,  Takashi Toyooka ,  Nobuo Saito

发明人： Shigeru Yoshizawa ,  Hirokazu Aoki ,  Shinsaku Chiba ,  Koichi Mayama ,  Takashi Toyooka ,  Nobuo Saito

IPC分类号： G11C19/08

CPC分类号： G11C19/085

摘要： The present invention provides an improved method and apparatus for driving a magnetic bubble device, in which a d-c voltage supply and drive coils are connected to a bridge circuit consisting of four bi-directional switches, and alternating currents with steps (such as currents consisting of triangular waves or trapezoidal waves) are produced in the drive coils by suitably controlling the turn on or off of the bi-directional switches. As a result, the d-c level in the alternating current is not shifted by the variation in width of pulses which control the opening and closing of the bi-directional switches, and the magnetic bubble device is provided with a greatly improved operation margin.

摘要翻译： 本发明提供了一种用于驱动磁性气泡装置的改进方法和装置，其中直流电压源和驱动线圈连接到由四个双向开关组成的桥接电路，并且具有步进的交流电（例如由 三角波或梯形波）通过适当地控制双向开关的导通或关断而在驱动线圈中产生。 结果，交流电流中的d-c电平不会由于控制双向开关的打开和关闭的脉冲宽度的变化而偏移，并且提供了大大改善的操作余量的磁性气泡装置。

公开(公告)号：US4550388A

公开(公告)日：1985-10-29

申请号：US636671

申请日：1984-08-01

申请人： Takashi Toyooka ,  Kazutoshi Yoshida ,  Kazuhiro Ishida ,  Tatsuo Okahashi ,  Hirokazu Aoki ,  Ryo Suzuki ,  Yutaka Sugita

发明人： Takashi Toyooka ,  Kazutoshi Yoshida ,  Kazuhiro Ishida ,  Tatsuo Okahashi ,  Hirokazu Aoki ,  Ryo Suzuki ,  Yutaka Sugita

IPC分类号： G11C11/14 ,  G11C19/08

CPC分类号： G11C19/085

摘要： In a magnetic bubble memory device in which magnetic bubbles are propagated under influence of a rotating magnetic field, a method of controlling a stop operation of a rotating magnetic field in which magnetic field is caused to further rotate beyond the stop direction for a predetermined over-rotation angle and is then caused to return to the stop direction which is followed by the removal of the magnetic field, is presented. The over-rotation angle is in a range of 10 to 40 degrees. The invention is applicable whether bubble drive is performed using a drive current of triangular, square or trapezoidal waveform.

摘要翻译： 在其中磁场在旋转磁场的影响下传播的磁性气泡存储装置中，一种控制使磁场进一步旋转超过停止方向的旋转磁场的停止操作的方法， 旋转角度，然后使其返回到停止方向，随后是去除磁场。 过旋转角度在10〜40度的范围内。 本发明适用于是否使用三角形，正方形或梯形波形的驱动电流进行气泡驱动。

公开(公告)号：US4530070A

公开(公告)日：1985-07-16

申请号：US505448

申请日：1983-06-17

申请人： Mamoru Sugie ,  Takashi Toyooka ,  Hirokazu Aoki

发明人： Mamoru Sugie ,  Takashi Toyooka ,  Hirokazu Aoki

IPC分类号： G11C11/14 ,  G11C19/08

CPC分类号： G11C19/0875

摘要： A magnetic bubble memory device including a magnetic bubble chip of major-minor structure is disclosed in which an integer m prime to the number n of bits of a minor loop is selected from integers i satisfying an equation i=(2.sup..alpha. .+-.1).multidot.2.sup..beta. +1 or i=(2.sup..alpha. .+-.1).multidot.2.sup..beta., and logical addresses on the minor loop are assigned in such a manner that adjacent logical addresses are spaced apart from each other by m bits.

摘要翻译： 公开了一种包括主要次要结构的磁性气泡芯片的磁性气泡存储装置，其中从满足等式i =（2α+/- 1）的整数i中选择小环的数目n的整数m素数 ）x2 beta +1或i =（2 alpha +/- 1）x2 beta，并且辅助环路上的逻辑地址以相邻逻辑地址彼此间隔m位的方式分配。

公开(公告)号：US4379341A

公开(公告)日：1983-04-05

申请号：US303527

申请日：1981-09-18

申请人： Takashi Toyooka ,  Mamoru Sugie ,  Hirokazu Aoki ,  Shigeru Yoshizawa

发明人： Takashi Toyooka ,  Mamoru Sugie ,  Hirokazu Aoki ,  Shigeru Yoshizawa

IPC分类号： G11C11/14 ,  G11C19/08

CPC分类号： G11C19/085

摘要： A series resonance drive circuit for a magnetic bubble memory comprises a magnetic bubble memory chip or chips, X and Y coils arranged orthogonally to each other to form a rotating magnetic field in a plane of the chip or chips, resonance capacitors connected in series with the X and Y coils to form series resonance circuits with the X and Y coils at a frequency of the rotating magnetic field, A.C. power supplies connected to the resonance circuit, and a reactance device connected to the resonance circuits to compensate a mutual inductance due to a mutual inductive coupling between the X and Y coils and a capacitance due to a capacitive coupling between the X and Y coils. The reactance device includes a mutual inductance device, or an inductance device and a capacitance device.

摘要翻译： 用于磁性气泡存储器的串联谐振驱动电路包括一个磁性气泡存储器芯片或芯片，彼此正交布置的X和Y线圈，以在芯片或芯片的平面中形成旋转磁场，与 X和Y线圈以与旋转磁场的频率成为X和Y线圈的串联谐振电路，连接到谐振电路的AC电源以及连接到谐振电路的电抗器件，以补偿由于 X和Y线圈之间的互感耦合以及由于X和Y线圈之间的电容耦合引起的电容。 电抗装置包括互感器件或电感器件和电容器件。

公开(公告)号：US06947514B1

公开(公告)日：2005-09-20

申请号：US09446507

申请日：1998-06-26

申请人： Kazuo Kato ,  Takashi Sase ,  Takashi Hotta ,  Hirokazu Aoki ,  Kozaburo Kurita

发明人： Kazuo Kato ,  Takashi Sase ,  Takashi Hotta ,  Hirokazu Aoki ,  Kozaburo Kurita

IPC分类号： H03L7/113 ,  H03D3/24 ,  H03L7/06

CPC分类号： H03L7/113

摘要： A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.

摘要翻译： 提供锁相环（PLL）电路以在宽带中操作，包括两个单独的环路，其中一个用于通过其关联比例控制单元将振荡器的输出反馈到同一个振荡器，而另一个 用于通过集成控制单元将振荡器的输出反馈到同一个振荡器。 比例控制单元被布置成控制振荡器的输出频率，并且可操作以基于输入和输出信号之间的差产生控制信号。 积分控制单元被布置成控制振荡器的输出信号的相位，从而基于输入和输出信号之间的相位差产生控制信号。