利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.036 秒)

    DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS
    3.
    发明申请
    DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 有权
    半导体存储器的DLL电路

    公开(公告)号：US20090002040A1

    公开(公告)日：2009-01-01

    申请号：US11964824

    申请日：2007-12-27

    申请人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H03L7/06

    CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

    摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.

    摘要翻译： 一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号 相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位 输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。

    PLL circuit having loop filter and method of driving the same
    4.
    发明申请
    PLL circuit having loop filter and method of driving the same 有权
    具有环路滤波器的PLL电路及其驱动方法

    公开(公告)号：US20080068058A1

    公开(公告)日：2008-03-20

    申请号：US11822103

    申请日：2007-07-02

    申请人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H03L7/085 ,  H03L7/08

    CPC分类号： H03L7/093 ,  H03L7/10

    摘要： A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.

    摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，并产生上拉控制信号和下拉控制信号。 环路滤波器根据上拉和下拉控制信号抽取电压，对泵浦电压进行滤波，并输出一个控制电压。 压控振荡器接收控制信号并振荡输出时钟。 时钟分频器以预定速率分频输出时钟的频率，以产生反馈时钟。 在PLL电路中，环路滤波器包括用于补偿变化的补偿器。

    Phase detecting circuit and clock generating apparatus including the same
    5.
    发明授权
    Phase detecting circuit and clock generating apparatus including the same 有权
    相位检测电路和包括该相位检测电路的时钟发生装置

    公开(公告)号：US07949081B2

    公开(公告)日：2011-05-24

    申请号：US12026384

    申请日：2008-02-05

    申请人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H04L7/04 ,  H03L7/00

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.

    摘要翻译： 相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及 充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。

    DUTY RATIO CORRECTION CIRCUIT
    6.
    发明申请
    DUTY RATIO CORRECTION CIRCUIT 审中-公开
    占空比校正电路

    公开(公告)号：US20090146700A1

    公开(公告)日：2009-06-11

    申请号：US12178475

    申请日：2008-07-23

    申请人： Yong Ju Kim ,  Kun Woo Park ,  Kyung Hoon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    发明人： Yong Ju Kim ,  Kun Woo Park ,  Kyung Hoon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03L7/07

    摘要： A duty ratio correction circuit including a reference clock generation block configured to generate first and second reference clocks that synchronize with rising and falling edges of an external clock and have a primarily corrected duty ratio, and a duty ratio adjustment block for generating first and second internal clocks in response to the first and second reference clocks, and secondarily correcting a duty ratio of the first and second reference clocks by adjusting phases of the first and second reference clocks by means of plural digital control signals generated according to phase difference between the first and second internal clocks.

    摘要翻译： 一种占空比校正电路，包括：参考时钟产生模块，被配置为产生与外部时钟的上升沿和下降沿同步并具有主要校正的占空比的第一和第二参考时钟;以及占空比调整块，用于产生第一和第二内部 响应于第一和第二参考时钟的时钟，并且通过根据根据第一和第二参考时钟的第一和第二参考时钟之间的相位差产生的多个数字控制信号来调整第一和第二参考时钟的占空比， 第二个内部时钟。

    PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME
    7.
    发明申请
    PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME 有权
    相位检测电路和时钟发生装置，包括它们

    公开(公告)号：US20090097608A1

    公开(公告)日：2009-04-16

    申请号：US12026384

    申请日：2008-02-05

    申请人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H04L7/00

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.

    摘要翻译： 相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及 充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。

    RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT
    8.
    发明申请
    RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
    在半导体集成电路中使用的接收器电路

    公开(公告)号：US20090058476A1

    公开(公告)日：2009-03-05

    申请号：US12171214

    申请日：2008-07-10

    申请人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    发明人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    IPC分类号： H03L7/00

    CPC分类号： H04L7/0337

    摘要： A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.

    摘要翻译： 一种接收机电路，用于与具有相互不同相位的多个时钟信号同步地感测和发送输入数据，其顺序地使能，包括读出放大器，其被配置为接收作为偏移电压的第一信号，所述第一信号可以通过与 所述多个时钟信号的第一时钟信号与与所述第一时钟信号之后使能的第二时钟信号同步地驱动，并输出第二信号;以及放电控制器，被配置为根据所述偏移来控制所述读出放大器的放电速度 电压来控制读出放大器的驱动速度。

    PLL circuit and method of controlling the same
    10.
    发明申请
    PLL circuit and method of controlling the same 失效
    PLL电路及其控制方法

    公开(公告)号：US20080068057A1

    公开(公告)日：2008-03-20

    申请号：US11819603

    申请日：2007-06-28

    申请人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H03L7/085 ,  H03L7/08

    CPC分类号： H03L7/0893 ,  H03L7/093 ,  H03L7/10

    摘要： A PLL circuit includes a phase detector that compares the phase of an input clock with the phase of a feedback clock so as to generate pull-up and pull-down control signals. A low pass filter pumps a voltage in response to the pull-up and pull-down control signals, and removes a noise component from the pumped voltage so as to output a control voltage. A buffer that controls voltage so as to generate a bias voltage having a smaller swing width than the control voltage. A voltage controlled oscillator receives the bias voltage and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined ratio so as to generate the feedback clock.

    摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，以产生上拉和下拉控制信号。 低通滤波器响应于上拉和下拉控制信号泵送电压，并从泵浦电压中去除噪声分量，以输出控制电压。 控制电压以产生具有比控制电压更小的摆动宽度的偏置电压的缓冲器。 压控振荡器接收偏置电压并振荡输出时钟。 时钟分频器以预定的比例对输出时钟的频率进行分频，以产生反馈时钟。