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23 条记录 (耗时 0.019 秒)

    Method for fabricating semiconductor device using amorphous carbon layer as sacrificial hard mask
    1.
    发明授权
    Method for fabricating semiconductor device using amorphous carbon layer as sacrificial hard mask 有权
    使用无定形碳层作为牺牲硬掩模制造半导体器件的方法

    公开(公告)号：US07446049B2

    公开(公告)日：2008-11-04

    申请号：US11149326

    申请日：2005-06-10

    申请人： Kwang-Ok Kim ,  Yun-Seok Cho

    发明人： Kwang-Ok Kim ,  Yun-Seok Cho

    IPC分类号： H01L21/311

    CPC分类号： H01L21/02115 ,  H01L21/0332 ,  H01L21/3146 ,  H01L21/32139

    摘要： Disclosed is a method for fabricating a semiconductor device by using an amorphous carbon layer as a sacrificial hard mask. The method includes the steps of: forming an amorphous carbon layer on an etch target layer; forming a photoresist pattern on the amorphous carbon layer; etching the amorphous carbon layer by using the photoresist pattern to form a sacrificial hard mask; and etching the etch target layer by using the sacrificial hard mask to form a predetermined pattern.

    摘要翻译： 公开了通过使用无定形碳层作为牺牲硬掩模来制造半导体器件的方法。 该方法包括以下步骤：在蚀刻目标层上形成无定形碳层; 在所述无定形碳层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案来蚀刻非晶碳层以形成牺牲硬掩模; 并通过使用牺牲硬掩模蚀刻蚀刻目标层以形成预定图案。

    Method for fabricating semiconductor device using amorphous carbon layer as sacrificial hard mask
    3.
    发明申请
    Method for fabricating semiconductor device using amorphous carbon layer as sacrificial hard mask 有权
    使用无定形碳层作为牺牲硬掩模制造半导体器件的方法

    公开(公告)号：US20060024945A1

    公开(公告)日：2006-02-02

    申请号：US11149326

    申请日：2005-06-10

    申请人： Kwang-Ok Kim ,  Yun-Seok Cho

    发明人： Kwang-Ok Kim ,  Yun-Seok Cho

    IPC分类号： H01L21/469

    CPC分类号： H01L21/02115 ,  H01L21/0332 ,  H01L21/3146 ,  H01L21/32139

    摘要： Disclosed is a method for fabricating a semiconductor device by using an amorphous carbon layer as a sacrificial hard mask. The method includes the steps of: forming an amorphous carbon layer on an etch target layer; forming a photoresist pattern on the amorphous carbon layer; etching the amorphous carbon layer by using the photoresist pattern to form a sacrificial hard mask; and etching the etch target layer by using the sacrificial hard mask to form a predetermined pattern.

    摘要翻译： 公开了通过使用无定形碳层作为牺牲硬掩模来制造半导体器件的方法。 该方法包括以下步骤：在蚀刻目标层上形成无定形碳层; 在所述无定形碳层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案来蚀刻非晶碳层以形成牺牲硬掩模; 并通过使用牺牲硬掩模蚀刻蚀刻目标层以形成预定图案。

    Method for forming metal line in semiconductor memory device having word line strapping structure
    5.
    发明申请
    Method for forming metal line in semiconductor memory device having word line strapping structure 审中-公开
    用于在具有字线捆扎结构的半导体存储器件中形成金属线的方法

    公开(公告)号：US20050287802A1

    公开(公告)日：2005-12-29

    申请号：US11019740

    申请日：2004-12-23

    申请人： Kwang-Ok Kim ,  Yun-Seok Cho

    发明人： Kwang-Ok Kim ,  Yun-Seok Cho

    IPC分类号： H01L21/28 ,  H01L21/3065 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76838 ,  H01L21/32139 ,  H01L27/10814 ,  H01L27/10891

    摘要： The present invention relates to a method for forming a metal line in a semiconductor memory device having a word strapping structure. Especially, the metal line is formed by using a dual hard mask including a tungsten layer and a nitride layer as an etch mask. Also, the metal line includes at least more than one metal layer based on a material selected from titanium nitride and aluminum. Furthermore, for the formation of the dual hard mask, a photoresist pattern to which an ArF photolithography process and a KrF photolithography process are applicable is used. The method includes the steps of: forming a metal structure on a substrate; forming a dual hard mask on the metal structure; forming a photoresist pattern on the dual hard mask; patterning the dual hard mask by using the photoresist pattern as an etch mask; and patterning the metal structure by using the dual hard mask, thereby obtaining the metal line.

    摘要翻译： 本发明涉及一种在具有字捆绑结构的半导体存储器件中形成金属线的方法。 特别地，通过使用包括钨层和氮化物层的双重硬掩模作为蚀刻掩模来形成金属线。 此外，金属线包括基于选自氮化钛和铝的材料的至少多于一个的金属层。 此外，为了形成双重硬掩模，使用可应用ArF光刻工艺和KrF光刻工艺的光致抗蚀剂图案。 该方法包括以下步骤：在衬底上形成金属结构; 在金属结构上形成双重硬掩模; 在双重硬掩模上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模来图案化双硬掩模; 并通过使用双硬掩模图案化金属结构，从而获得金属线。

    SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME 有权
    带有双绞线的半导体器件及其制造方法

    公开(公告)号：US20110101447A1

    公开(公告)日：2011-05-05

    申请号：US12649107

    申请日：2009-12-29

    申请人： Yun-Seok Cho

    发明人： Yun-Seok Cho

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336

    CPC分类号： H01L27/10885 ,  H01L27/10876 ,  H01L27/10891

    摘要： A semiconductor device includes a substrate having trenches, buried bit lines formed in the substrate, and including a metal silicide layer and a metallic layer, wherein the metal silicide layer contacts sidewalls of the trenches and the metallic layer is formed over the sidewalls of the trenches and contacts the metal silicide layer.

    摘要翻译： 半导体器件包括具有沟槽的基板，在基板中形成的掩埋位线，并且包括金属硅化物层和金属层，其中金属硅化物层接触沟槽的侧壁和金属层形成在沟槽的侧壁上 并与金属硅化物层接触。

    Semiconductor device with buried bit lines and method for fabricating the same
    8.
    发明授权
    Semiconductor device with buried bit lines and method for fabricating the same 有权
    具有掩埋位线的半导体器件及其制造方法

    公开(公告)号：US08169020B2

    公开(公告)日：2012-05-01

    申请号：US12649107

    申请日：2009-12-29

    申请人： Yun-Seok Cho

    发明人： Yun-Seok Cho

    IPC分类号： H01L29/78

    CPC分类号： H01L27/10885 ,  H01L27/10876 ,  H01L27/10891

    摘要： A semiconductor device includes a substrate having trenches, buried bit lines formed in the substrate, and including a metal silicide layer and a metallic layer, wherein the metal silicide layer contacts sidewalls of the trenches and the metallic layer is formed over the sidewalls of the trenches and contacts the metal silicide layer.

    摘要翻译： 半导体器件包括具有沟槽的基板，在基板中形成的掩埋位线，并且包括金属硅化物层和金属层，其中金属硅化物层接触沟槽的侧壁和金属层形成在沟槽的侧壁上 并与金属硅化物层接触。

    Method of fabricating semiconductor device for preventing a pillar pattern from bending and from exposing externally
    9.
    发明授权
    Method of fabricating semiconductor device for preventing a pillar pattern from bending and from exposing externally 有权
    制造用于防止柱状图案弯曲并从外部暴露的半导体器件的方法

    公开(公告)号：US07829415B2

    公开(公告)日：2010-11-09

    申请号：US12336369

    申请日：2008-12-16

    申请人： Yun-Seok Cho ,  Young-Kyun Jung ,  Chun-Hee Lee

    发明人： Yun-Seok Cho ,  Young-Kyun Jung ,  Chun-Hee Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L29/7827

    摘要： A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成多个柱状图案，用第一导电层填充柱状图案之间的间隙，在与一个方向相邻的柱状图案上形成第一硬掩模层图案，蚀刻第一 使用所述第一硬掩模层图案作为蚀刻阻挡层，在与所述一个方向交叉的另一个方向上相邻的所述柱图案上形成第二硬掩模图案，以及通过蚀刻所述第一导电层形成围绕所述柱图案的栅电极 使用第二硬掩模层图案蚀刻作为蚀刻阻挡层。

    Semiconductor device and method of fabricating the same
    10.
    发明申请
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20090242945A1

    公开(公告)日：2009-10-01

    申请号：US12318165

    申请日：2008-12-23

    申请人： Yun-Seok Cho ,  Sang-Hoon Park ,  Young-Kyun Jung ,  Chun-Hee Lee

    发明人： Yun-Seok Cho ,  Sang-Hoon Park ,  Young-Kyun Jung ,  Chun-Hee Lee

    IPC分类号： H01L29/78 ,  H01L21/4763

    CPC分类号： H01L29/66666 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966

    摘要： In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each pillar pattern, and the gate electrode is formed by etching the conductive pattern using the spacer as an etch barrier.

    摘要翻译： 在具有柱状图案的基板上制造半导体器件的方法中，在柱状图案上形成栅电极而不对其进行蚀刻。 导电图形填充在相邻的柱图案之间，在导电图案上方形成间隔物，并且在每个柱图案的周围形成围绕的侧壁，并且通过使用间隔物作为蚀刻阻挡层蚀刻导电图案来形成栅电极。