公开(公告)号：US06170235B2

公开(公告)日：2001-01-09

申请号：US09206234

申请日：1998-12-07

申请人： Kyoo-chul Cho ,  Jea-gun Park ,  Sung-hoon Cho

发明人： Kyoo-chul Cho ,  Jea-gun Park ,  Sung-hoon Cho

IPC分类号： B65B5500

CPC分类号： H01L21/67353 ,  H01L21/67386

摘要： A wafer packaging method in which a wafer is placed into a packaging bag that is sealed before the concentration of sulphuric oxide on the surface of the wafer reaches 3×1012 atoms/cm2. The placing of the wafer in the wafer packaging bag is carried out in a substantially clean environment

摘要翻译： 一种晶片封装方法，其中将晶片放置在在晶片表面上的硫酸氧化物的浓度达到3×10 12原子/ cm 2之前密封的包装袋中。 在晶片包装袋中放置晶片在基本上清洁的环境中进行

公开(公告)号：US6045610A

公开(公告)日：2000-04-04

申请号：US989591

申请日：1997-12-12

申请人： Jea-gun Park ,  Kyoo-chul Cho ,  Gon-sub Lee

发明人： Jea-gun Park ,  Kyoo-chul Cho ,  Gon-sub Lee

IPC分类号： C30B15/00 ,  C30B15/14 ,  C30B15/20

CPC分类号： C30B29/06 ,  C30B15/14 ,  C30B15/203 ,  Y10T117/1004 ,  Y10T117/1008

摘要： A silicon ingot is manufactured in a hot zone furnace by pulling the ingot from a silicon melt in the hot zone furnace in an axial direction, at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates but is sufficiently low so as to confine vacancy agglomerates to a vacancy rich region at the axis of the ingot. The ingot so pulled is sliced into a plurality of semi-pure wafers each having a vacancy rich region at the center thereof that includes vacancy agglomerates and a pure region between the vacancy rich region and the wafer edge that is free of vacancy agglomerates and interstitial agglomerates. According to another aspect of the present invention, the ingot is pulled from the silicon melt in the hot zone furnace at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates, but is also sufficiently low as to prevent vacancy agglomerates. Accordingly, when this ingot is sliced into wafers, the wafers are pure silicon wafers that may include point defects but that are free of vacancy agglomerates and interstitial agglomerates.

摘要翻译： 在热区炉中通过从热区炉中的硅熔体在轴向方向上以锭子的拉力速率分布从热区炉中的硅熔体中提取足够高的硅锭来制造硅锭 以防止间隙附聚物但足够低以便将空位团聚物限制在锭的轴线处的空位丰富区域。 将如此拉出的锭切成多个半纯晶片，每个半晶片在其中心处具有空位丰富区域，其包括空位团聚体和在空位富集区域和晶片边缘之间的纯区域，其中没有空隙附聚物和间隙附聚物 。 根据本发明的另一方面，将铸锭从热区炉中的硅熔体中以锭的拉伸速率分布从热区炉中的硅熔体中提取得足够高以防止间隙附聚物， 但也足够低以防止空位聚集。 因此，当该锭被切成晶片时，晶片是纯硅晶片，其可以包括点缺陷，但是没有空隙聚集体和间隙附聚物。

公开(公告)号：US06472040B1

公开(公告)日：2002-10-29

申请号：US09454675

申请日：1999-12-03

申请人： Jea-gun Park ,  Kyoo-chul Cho ,  Gon-sub Lee

发明人： Jea-gun Park ,  Kyoo-chul Cho ,  Gon-sub Lee

IPC分类号： C30B2906

CPC分类号： C30B29/06 ,  C30B15/14 ,  C30B15/203 ,  Y10S117/90 ,  Y10S117/911 ,  Y10T117/10 ,  Y10T117/1004 ,  Y10T117/1032 ,  Y10T117/1052 ,  Y10T117/1068 ,  Y10T117/1072 ,  Y10T117/1088 ,  Y10T428/21

摘要： A silicon ingot is manufactured in a hot zone furnace by pulling the ingot from a silicon melt in the hot zone furnace in an axial direction, at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates but is sufficiently low so as to confine vacancy agglomerates to a vacancy rich region at the axis of the ingot. The ingot so pulled is sliced into a plurality of semi-pure wafers each having a vacancy rich region at the center thereof that includes vacancy agglomerates and a pure region between the vacancy rich region and the wafer edge that is free of vacancy agglomerates and interstitial agglomerates. According to another aspect of the present invention, the ingot is pulled from the silicon melt in the hot zone furnace at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates, but is also sufficiently low as to prevent vacancy agglomerates. Accordingly, when this ingot is sliced into wafers, the wafers are pure silicon wafers that may include point defects but that are free of vacancy agglomerates and interstitial agglomerates.

摘要翻译： 在热区炉中通过从热区炉中的硅熔体在轴向方向上以锭子的拉力速率分布从热区炉中的硅熔体中提取足够高的硅锭来制造硅锭 以防止间隙附聚物但足够低以便将空位团聚物限制在锭的轴线处的空位丰富区域。 将如此拉出的锭切成多个半纯晶片，每个半晶片在其中心处具有空位丰富区域，其包括空位团聚体和在空位富集区域和晶片边缘之间的纯区域，其中没有空隙附聚物和间隙附聚物 。 根据本发明的另一方面，将铸锭从热区炉中的硅熔体中以锭的拉伸速率分布从热区炉中的硅熔体中提取得足够高以防止间隙附聚物， 但也足够低以防止空位聚集。 因此，当该锭被切成晶片时，晶片是纯硅晶片，其可以包括点缺陷，但是没有空隙聚集体和间隙附聚物。

公开(公告)号：US20090236655A1

公开(公告)日：2009-09-24

申请号：US12468414

申请日：2009-05-19

申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

公开(公告)号：US07550347B2

公开(公告)日：2009-06-23

申请号：US11510059

申请日：2006-08-25

申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成具有小于约0.5厘米每秒（cm 2 / s）的热扩散率的离子，从而在第一电介质层中形成电荷存储区， 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

公开(公告)号：US20070128846A1

公开(公告)日：2007-06-07

申请号：US11510059

申请日：2006-08-25

申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一介电层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，从而形成电荷存储 区域，在电荷存储区域下方具有隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

公开(公告)号：US5944889A

公开(公告)日：1999-08-31

申请号：US978937

申请日：1997-11-26

申请人： Jae-guen Park ,  Gon-sub Lee ,  Kyoo-chul Cho ,  Ho-kyoon Chung

发明人： Jae-guen Park ,  Gon-sub Lee ,  Kyoo-chul Cho ,  Ho-kyoon Chung

IPC分类号： H01L21/324 ,  H01L21/322 ,  C30B25/20

CPC分类号： H01L21/3225

摘要： With a view to optimizing the donor killing process performed in the semiconductor wafer fabricating process, a heat-treating operation is performed in a thermal furnace above at least 900 .degree. C. for a predetermined time so that growth of the initial oxygen precipitates, induced into the crystal lattices during single-crystal growth, is suppressed. Thus, the oxygen precipitates are easily suppressed, irrespective of the concentration of the initial oxygen, so that the yield of the semiconductor device is improved

摘要翻译： 为了优化在半导体晶片制造工艺中进行的供体杀死过程，在热处理炉中，在高于至少900℃的温度下进行预定时间的热处理操作，使得初始氧沉淀物的生长被诱导成 单晶生长期间的晶格被抑制。 因此，不管初始氧的浓度如何，容易抑制氧析出物，从而提高半导体器件的产率

公开(公告)号：US09035309B2

公开(公告)日：2015-05-19

申请号：US12984972

申请日：2011-01-05

申请人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

发明人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

IPC分类号： H01L27/146

CPC分类号： H01L27/14629 ,  H01L27/14687

摘要： A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

摘要翻译： 一种三维（3D）CMOS图像传感器（CIS），其足以吸收入射的红外线（IR）并且包括形成在薄的外延膜中的红外线（IR）接收单元，由此容易地使用传统的CIS工艺 包括3D CIS的传感器系统和制造3D CIS的方法，3D CIS包括通过重复反射吸收入射到其中的IR的IR接收部分以产生电子 - 空穴对（EHP）; 以及形成在IR接收部上并且收集通过施加预定电压而产生的电子的电极部分。

公开(公告)号：US06552337B1

公开(公告)日：2003-04-22

申请号：US09688283

申请日：2000-10-13

申请人： Kyoo-chul Cho ,  Tae-Yeol Heo ,  Jeong-hoon An ,  Gi-jung Kim

发明人： Kyoo-chul Cho ,  Tae-Yeol Heo ,  Jeong-hoon An ,  Gi-jung Kim

IPC分类号： H01J3726

CPC分类号： G01Q60/24 ,  G01B7/34 ,  G01Q30/02 ,  H01L22/12 ,  Y10S977/852

摘要： Embodiments of the present invention provide methods for measuring a wafer surface. A portion of the wafer surface is measured using a particle counter to provide first measurements corresponding to a plurality of points on the wafer surface. A selected area of the wafer surface including one of the plurality of points is measured using an atomic force microscope (AFM) to provide a microroughness measurement of the selected area. The selected area is a localized area of the portion of the wafer surface measured using the particle counter. The first measurements and the microroughness measurement are provided as a measurement of the wafer surface. The portion measured using a particle counter may, for example, be substantially the entire wafer surface.

摘要翻译： 本发明的实施例提供了用于测量晶片表面的方法。 使用粒子计数器测量晶片表面的一部分，以提供对应于晶片表面上的多个点的第一测量。 使用原子力显微镜（AFM）测量包括多个点中的一个的晶片表面的选定区域，以提供所选区域的微粗糙度测量。 所选择的区域是使用粒子计数器测量的晶片表面部分的局部区域。 提供第一测量和微粗糙度测量作为晶片表面的测量。 使用粒子计数器测量的部分可以例如基本上是整个晶片表面。

公开(公告)号：US07964907B2

公开(公告)日：2011-06-21

申请号：US12468414

申请日：2009-05-19

申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。