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    Methods for forming a metal layer on a semiconductor
    1.
    发明授权
    Methods for forming a metal layer on a semiconductor 有权
    在半导体上形成金属层的方法

    公开(公告)号：US07067420B2

    公开(公告)日：2006-06-27

    申请号：US10404360

    申请日：2003-04-01

    申请人： Kyung-In Choi ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Sang-Bum Kang

    发明人： Kyung-In Choi ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Sang-Bum Kang

    IPC分类号： H10L21/4763 ,  H10L21/20 ,  H10L21/44

    CPC分类号： H01L21/76843 ,  C23C16/34 ,  C23C16/45542 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76877

    摘要： A metal layer is formed on an integrated circuit device including forming an insulating layer on an integrated circuit substrate. A contact hole is formed by selectively etching the insulating layer to thereby partially expose the substrate. A metal layer including tantalum nitride is formed on the insulating layer including the contact hole using a tantalum precursor including a tantalum element and at least one bonding element that is chemically bonded to the tantalum element. A part of the at least one bonding element include at least one ligand bonding element that is ligand-bonded to the tantalum element. Forming the metal layer may include removing at least some of the ligand bonded elements with a removing gas that is substantially free of hydrogen radicals. The metal layer may be formed using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. A copper or other metal layer may be deposited on the metal layer including tantalum nitride.

    摘要翻译： 金属层形成在集成电路器件上，包括在集成电路衬底上形成绝缘层。 通过选择性地蚀刻绝缘层从而部分地暴露衬底而形成接触孔。 包括氮化钽的金属层使用包括钽元素的钽前体和与钽元素化学键合的至少一个结合元件在包括接触孔的绝缘层上形成。 至少一个键合元件的一部分包括与钽元素配位键合的至少一个配体结合元件。 形成金属层可以包括用基本上不含氢自由基的去除气体去除至少一些配体键合元件。 可以使用化学气相沉积（CVD）或原子层沉积（ALD）工艺来形成金属层。 可以在包括氮化钽的金属层上沉积铜或其它金属层。

    Methods of forming electronic devices including high-K dielectric layers and electrode barrier layers and related structures
    2.
    发明申请
    Methods of forming electronic devices including high-K dielectric layers and electrode barrier layers and related structures 有权
    形成包括高K电介质层和电极阻挡层及相关结构的电子器件的方法

    公开(公告)号：US20060263966A1

    公开(公告)日：2006-11-23

    申请号：US11479551

    申请日：2006-06-30

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

    摘要翻译： 形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。 可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。 栅电极阻挡层和栅电极金属层可以由不同的材料形成。 此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

    Semiconductor interconnection structure with TaN and method of forming the same
    4.
    发明申请
    Semiconductor interconnection structure with TaN and method of forming the same 审中-公开
    具有TaN的半导体互连结构及其形成方法

    公开(公告)号：US20050136652A1

    公开(公告)日：2005-06-23

    申请号：US11046624

    申请日：2005-01-28

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/7685 ,  H01L21/76802 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a semiconductor substrate. According to the method of forming the structure, a tantalum nitride layer is formed by using a PVD, CVD, or ALD process and patterned to form a tantalum nitride layer pattern. The structure and the method prevents process failures such as ring defects, simplifies associated processes, and allows relatively easy exposure of only an anti-refractive layer when forming a via hole in the structure.

    摘要翻译： 结构包括依次层叠在半导体衬底上的扩散阻挡层图案，导电层图案，粘合层图案和氮化钽层图案。 根据形成结构的方法，通过使用PVD，CVD或ALD工艺形成氮化钽层并且被图案化以形成氮化钽层图案。 结构和方法防止诸如环形缺陷的过程故障，简化相关工艺，并且当在结构中形成通孔时，仅允许抗折射层相对容易地曝光。

    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers
    5.
    发明申请
    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers 有权
    形成包括高k电介质层和电极阻挡层的电子器件的方法

    公开(公告)号：US20050082625A1

    公开(公告)日：2005-04-21

    申请号：US10969564

    申请日：2004-10-20

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

    摘要翻译： 形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。 可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。 栅电极阻挡层和栅电极金属层可以由不同的材料形成。 此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers and related structures
    7.
    发明授权
    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers and related structures 有权
    形成包括高k电介质层和电极阻挡层以及相关结构的电子器件的方法

    公开(公告)号：US07244645B2

    公开(公告)日：2007-07-17

    申请号：US11479551

    申请日：2006-06-30

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

    摘要翻译： 形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。 可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。 栅电极阻挡层和栅电极金属层可以由不同的材料形成。 此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers
    8.
    发明授权
    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers 有权
    形成包括高k电介质层和电极阻挡层的电子器件的方法

    公开(公告)号：US07148100B2

    公开(公告)日：2006-12-12

    申请号：US10969564

    申请日：2004-10-20

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

    摘要翻译： 形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。 可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。 栅电极阻挡层和栅电极金属层可以由不同的材料形成。 此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

    Methods of forming dual gate semiconductor devices having a metal nitride layer
    10.
    发明授权
    Methods of forming dual gate semiconductor devices having a metal nitride layer 有权
    形成具有金属氮化物层的双栅极半导体器件的方法

    公开(公告)号：US06815285B2

    公开(公告)日：2004-11-09

    申请号：US10425276

    申请日：2003-04-29

    申请人： Gil-Heyun Choi ,  Jong-Ho Lee ,  Kyung-In Choi ,  Byung-Hee Kim

    发明人： Gil-Heyun Choi ,  Jong-Ho Lee ,  Kyung-In Choi ,  Byung-Hee Kim

    IPC分类号： H01L218238

    CPC分类号： H01L21/28185 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A method for forming a dual gate includes providing a semiconductor substrate that has a first region of a first conductivity type and a second region of a second conductivity type. A gate insulating layer is formed on the semiconductor substrate. An initial metal nitride layer is formed on the gate insulating layer, opposite to the semiconductor substrate. Nitrogen ions are implanted into the initial metal nitride layer in the second transistor region to form a nitrogen-rich metal nitride layer. The initial metal nitride layer is patterned to form a first gate electrode in the first region. The nitrogen-rich metal nitride layer is patterned to form a second gate electrode in the second region. The work function of the nitrogen-rich metal nitride layer is higher than that of the initial metal nitride layer.

    摘要翻译： 形成双栅极的方法包括提供具有第一导电类型的第一区域和第二导电类型的第二区域的半导体衬底。 在半导体衬底上形成栅极绝缘层。 在栅极绝缘层上形成与半导体衬底相反的初始金属氮化物层。 将氮离子注入到第二晶体管区域中的初始金属氮化物层中以形成富氮金属氮化物层。 图案化初始金属氮化物层以在第一区域中形成第一栅电极。 图案化富氮金属氮化物层以在第二区域中形成第二栅电极。 富氮金属氮化物层的功函数高于初始金属氮化物层的功函数。