公开(公告)号：US20120009781A1

公开(公告)日：2012-01-12

申请号：US13240109

申请日：2011-09-22

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 在第一阻挡层的暴露部分上进行氮化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US08304343B2

公开(公告)日：2012-11-06

申请号：US13240109

申请日：2011-09-22

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 在第一阻挡层的暴露部分上进行氮化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US08053374B2

公开(公告)日：2011-11-08

申请号：US12506361

申请日：2009-07-21

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitidation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 对第一阻挡层的暴露部分进行硝化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US20100022086A1

公开(公告)日：2010-01-28

申请号：US12506361

申请日：2009-07-21

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitidation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 对第一阻挡层的暴露部分进行硝化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US06905960B2

公开(公告)日：2005-06-14

申请号：US10657140

申请日：2003-09-09

申请人： Hong-Mi Park ,  Jong-Sik Chun ,  Hyeon-Deok Lee ,  In-Sun Park ,  Jong-Myeong Lee ,  Ju-Cheol Shin

发明人： Hong-Mi Park ,  Jong-Sik Chun ,  Hyeon-Deok Lee ,  In-Sun Park ,  Jong-Myeong Lee ,  Ju-Cheol Shin

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76843 ,  H01L21/76871

摘要： In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.

摘要翻译： 在半导体器件中形成接触的方法中，在半导体衬底上形成绝缘层。 然后，通过选择性地蚀刻绝缘层形成接触孔。 阻挡金属层沉积在接触孔的侧表面和底表面上，并且在绝缘层的顶表面上沉积到均匀的厚度。 在阻挡金属层上沉积抗氧化金属材料的润湿层。 在润湿层上形成金属层，并填充接触孔，从而在半导体器件中形成接触。

公开(公告)号：US06673718B1

公开(公告)日：2004-01-06

申请号：US10305244

申请日：2002-11-27

申请人： Jong-Myeong Lee ,  In-Sun Park ,  Hyeon-Deok Lee ,  Jong-Sik Chun

发明人： Jong-Myeong Lee ,  In-Sun Park ,  Hyeon-Deok Lee ,  Jong-Sik Chun

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.

摘要翻译： 在基板的接触孔或凹槽内选择性地形成铝布线。 包含氮的中间层形成在基板的主表面上并在接触孔或凹槽的内表面上方。 用等离子体处理位于基板的主表面上方的中间层的第一表面部分，以在中间层的第一表面部分处形成被动层。 然后，没有中间真空断裂，铝膜仅沉积在中间层的位于接触孔或凹槽的内表面上方的第二表面部分上。 中间层的第一表面部分的等离子体处理防止铝膜在中间层的第一表面部分上的CAD沉积。

公开(公告)号：US07410869B2

公开(公告)日：2008-08-12

申请号：US11480380

申请日：2006-07-05

申请人： Hun-Hyeoung Leam ,  Hyeon-Deok Lee ,  Young-Sub You ,  Won-Jun Jang ,  Woong Lee ,  Jung-Hyun Park ,  Sang-Kyoung Lee ,  Jung-Geun Jee ,  Sang-Hoon Lee

发明人： Hun-Hyeoung Leam ,  Hyeon-Deok Lee ,  Young-Sub You ,  Won-Jun Jang ,  Woong Lee ,  Jung-Hyun Park ,  Sang-Kyoung Lee ,  Jung-Geun Jee ,  Sang-Hoon Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/32115 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.

摘要翻译： 在制造诸如闪速存储器件的半导体器件的方法中，形成具有开口的绝缘图案以部分地暴露衬底的表面。 第一硅层形成在基板的露出表面部分和绝缘图案上。 第一硅层具有覆盖衬底的先前暴露部分的开口接缝。 在足以诱导硅迁移的温度下进行在基板上的热处理，以便通过硅迁移使开放的接缝闭合。 然后在第一硅层上形成第二硅层。 因此，可以提高从第一和第二硅层获得的浮栅的表面轮廓。

公开(公告)号：US07311109B2

公开(公告)日：2007-12-25

申请号：US10606512

申请日：2003-06-26

申请人： Jung-wook Kim ,  Hyeon-Deok Lee ,  Jin-Gi Hong ,  Ji-Soon Park ,  Eung-Joon Lee

发明人： Jung-wook Kim ,  Hyeon-Deok Lee ,  Jin-Gi Hong ,  Ji-Soon Park ,  Eung-Joon Lee

IPC分类号： B08B9/00 ,  H01L21/00

CPC分类号： C23C16/4405 ,  C23C16/0245 ,  H01L21/02063 ,  H01L21/76814 ,  Y10S438/905

摘要： A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.

摘要翻译： 一种清洗处理室的方法，并且利用包含氢气的第一气体的等离子体从处理室中的基板上除去杂质来制造半导体器件。 在从处理室移除基板之后，用非氢气的第二气体的等离子体蚀刻处理室。 因此，可以提高蚀刻选择性，并且防止颗粒在衬底上沉积和/或形成。

公开(公告)号：US07238585B2

公开(公告)日：2007-07-03

申请号：US11516707

申请日：2006-09-07

申请人： Kyoung-Seok Kim ,  Ki-Hyun Hwang ,  Hyo-Jung Kim ,  Hyeon-Deok Lee ,  Seok-Woo Nam

发明人： Kyoung-Seok Kim ,  Ki-Hyun Hwang ,  Hyo-Jung Kim ,  Hyeon-Deok Lee ,  Seok-Woo Nam

IPC分类号： H01L21/20

CPC分类号： H01L28/84 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/90

摘要： In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.

公开(公告)号：US07122468B2

公开(公告)日：2006-10-17

申请号：US11039562

申请日：2005-01-20

申请人： Ju-Cheol Shin ,  Hyeon-Deok Lee ,  Hong-Mi Park ,  In-Sun Park

发明人： Ju-Cheol Shin ,  Hyeon-Deok Lee ,  Hong-Mi Park ,  In-Sun Park

IPC分类号： H01L21/4763

CPC分类号： H01L27/10894 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/10817 ,  H01L27/10885 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a substrate and a first insulating layer on the substrate that includes a first hole including a floor and a sidewall. A first conductive contact extends conformally on the sidewall and floor to define a groove in the first hole. A second insulating layer is provided on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is provided in the second hole and in the groove. These integrated circuits are fabricated by forming a first insulating layer on a substrate that includes a first hole including a floor and a sidewall. A first conductive contact is conformally formed on the sidewall and floor to define a groove in the first hole. A second insulating layer is formed on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is formed in the second hole and in the groove.

摘要翻译： 集成电路包括衬底和衬底上的第一绝缘层，其包括包括地板和侧壁的第一孔。 第一导电接触件在侧壁和底板上保形地延伸以在第一孔中限定凹槽。 第二绝缘层设置在第一绝缘层上，并且包括露出槽的第二孔。 在第二孔和凹槽中设置第二导电接触。 这些集成电路通过在基板上形成第一绝缘层来制造，所述第一绝缘层包括包括地板和侧壁的第一孔。 第一导电接触共形地形成在侧壁和地板上以在第一孔中限定凹槽。 第二绝缘层形成在第一绝缘层上，并且包括暴露槽的第二孔。 在第二孔和槽中形成第二导电接触。