公开(公告)号：US20140302678A1

公开(公告)日：2014-10-09

申请号：US14184491

申请日：2014-02-19

Applicant: LAM RESEARCH CORPORATION

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/3065

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。 离子离子等离子体可以用于各种蚀刻工艺中。

公开(公告)号：US11170997B2

公开(公告)日：2021-11-09

申请号：US16845746

申请日：2020-04-10

Applicant: Lam Research Corporation

Inventor： Xiang Zhou ,  Naveed Ansari ,  Yoshie Kimura ,  Si-Yi Yi Li ,  Kazi Sultana ,  Radhika Mani ,  Duming Zhang ,  Haseeb Kazi ,  Chen Xu ,  Mitchell Brooks ,  Ganesh Upadhyaya

IPC: H01L21/02 ,  H01L21/473 ,  H01L21/033 ,  H01L21/768 ,  H01L21/308 ,  H01L29/78

Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

公开(公告)号：US20200243326A1

公开(公告)日：2020-07-30

申请号：US16845746

申请日：2020-04-10

Applicant: Lam Research Corporation

Inventor： Xiang Zhou ,  Naveed Ansari ,  Yoshie Kimura ,  Si-Yi Yi Li ,  Kazi Sultana ,  Radhika Mani ,  Duming Zhang ,  Haseeb Kazi ,  Chen Xu ,  Mitchell Brooks ,  Ganesh Upadhyaya

IPC: H01L21/02 ,  H01L21/473 ,  H01L21/033 ,  H01L21/768 ,  H01L21/308 ,  H01L29/78

Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

公开(公告)号：US20160086795A1

公开(公告)日：2016-03-24

申请号：US14954586

申请日：2015-11-30

Applicant: Lam Research Corporation

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。 离子离子等离子体可以用于各种蚀刻工艺中。

公开(公告)号：US09230819B2

公开(公告)日：2016-01-05

申请号：US14184491

申请日：2014-02-19

Applicant: Lam Research Corporation

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/00 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。 离子离子等离子体可以用于各种蚀刻工艺中。

公开(公告)号：US10658174B2

公开(公告)日：2020-05-19

申请号：US15820110

申请日：2017-11-21

Applicant: Lam Research Corporation

Inventor： Xiang Zhou ,  Naveed Ansari ,  Yoshie Kimura ,  Si-Yi Yi Li ,  Kazi Sultana ,  Radhika Mani ,  Duming Zhang ,  Haseeb Kazi ,  Chen Xu ,  Mitchell Brooks ,  Ganesh Upadhyaya

IPC: H01L21/02 ,  H01L21/473 ,  H01L21/033 ,  H01L21/768 ,  H01L21/308 ,  H01L29/78

Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

公开(公告)号：US20190157066A1

公开(公告)日：2019-05-23

申请号：US15820110

申请日：2017-11-21

Applicant: Lam Research Corporation

Inventor： Xiang Zhou ,  Naveed Ansari ,  Yoshie Kimura ,  Si-Yi Yi Li ,  Kazi Sultana ,  Radhika Mani ,  Duming Zhang ,  Haseeb Kazi ,  Chen Xu ,  Mitchell Brooks ,  Ganesh Upadhyaya

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/033 ,  H01L21/473

Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

公开(公告)号：US09633846B2

公开(公告)日：2017-04-25

申请号：US14954586

申请日：2015-11-30

Applicant: Lam Research Corporation

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/00 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.