公开(公告)号：US20180240677A1

公开(公告)日：2018-08-23

申请号：US15959135

申请日：2018-04-20

Applicant: Lam Research Corporation

Inventor： Saravanapriyan Sriraman ,  Monica Titus ,  Alex Paterson

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/67 ,  C23C16/455 ,  H01L21/31

CPC classification number: H01L21/3065 ,  C23C16/45561 ,  C23C16/45574 ,  H01J37/321 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32926 ,  H01L21/31 ,  H01L21/67069

Abstract: Methods, systems, and computer programs are presented for controlling gas flow in a semiconductor manufacturing chamber. The method includes flowing a reactant gas thorough an inner feed and a tuning gas through an outer feed surrounding the inner feed, such that the gases do not mix until both are introduced in the chamber. Further, the flow of the reactant gas is convective, and the flow of the tuning gas is directed at an angle from the direction of the reactant gas, providing a delivery of the tuning gas in closer proximity to the RF power before further mixing with the reactant gas. Radio frequency power is provided to the electrode to ignite a plasma using the reactant and tuning gases. The diffusive flow of the tuning gas enables the tuning gas to be dissociated by the RF power allowing for control of the local residence time variation and preferential spatial dissociation patterns with respect to the local residence time of the reactant gas. The introduction of the gases into the chamber without pre-mixing imparts control of etch uniformity across the surface of the substrate during etching.

公开(公告)号：US09633846B2

公开(公告)日：2017-04-25

申请号：US14954586

申请日：2015-11-30

Applicant: Lam Research Corporation

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/00 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

公开(公告)号：US09966270B2

公开(公告)日：2018-05-08

申请号：US14675659

申请日：2015-03-31

Applicant: Lam Research Corporation

Inventor： Saravanapriyan Sriraman ,  Monica Titus ,  Alex Paterson

IPC: H01L21/3065 ,  C23C16/455 ,  H01J37/32 ,  H01L21/31 ,  H01L21/67

CPC classification number: H01L21/3065 ,  C23C16/45561 ,  C23C16/45574 ,  H01J37/321 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32926 ,  H01L21/31 ,  H01L21/67069

Abstract: Methods, systems, and computer programs are presented for controlling gas flow in a semiconductor manufacturing chamber. The method includes flowing a reactant gas thorough an inner feed and a tuning gas through an outer feed surrounding the inner feed, such that the gases do not mix until both are introduced in the chamber. Further, the flow of the reactant gas is convective, and the flow of the tuning gas is directed at an angle from the direction of the reactant gas, providing a delivery of the tuning gas in closer proximity to the RF power before further mixing with the reactant gas. Radio frequency power is provided to the electrode to ignite a plasma using the reactant and tuning gases.

公开(公告)号：US09245761B2

公开(公告)日：2016-01-26

申请号：US13916318

申请日：2013-06-12

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Thorsten Lill ,  Vahid Vahedi ,  Alex Paterson ,  Monica Titus ,  Gowri Kamarthy

IPC: C23C16/00 ,  H01L21/306 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/67069 ,  H01J37/32009 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32633 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在使用多个等离子体栅格的情况下，一个或多个栅格可以是可移动的，允许在至少下部子室中等离子体条件的稳定性。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。

公开(公告)号：US20140302680A1

公开(公告)日：2014-10-09

申请号：US13916318

申请日：2013-06-12

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Thorsten Lill ,  Vahid Vahedi ,  Alex Paterson ,  Monica Titus ,  Gowri Kamarthy

IPC: H01L21/3065 ,  H01L21/67

CPC classification number: H01L21/67069 ,  H01J37/32009 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32633 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在使用多个等离子体栅格的情况下，一个或多个栅格可以是可移动的，允许至少在下部子室中的等离子体条件的稳定性。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。

公开(公告)号：US20140302678A1

公开(公告)日：2014-10-09

申请号：US14184491

申请日：2014-02-19

Applicant: LAM RESEARCH CORPORATION

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/3065

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。 离子离子等离子体可以用于各种蚀刻工艺中。

公开(公告)号：US09589853B2

公开(公告)日：2017-03-07

申请号：US14337953

申请日：2014-07-22

Applicant: Lam Research Corporation

Inventor： Monica Titus ,  Gowri Kamarthy ,  Harmeet Singh ,  Yoshie Kimura ,  Meihua Shen ,  Baosuo Zhou ,  Yifeng Zhou ,  John Hoang

IPC: H01L21/00 ,  H01L21/3065 ,  H01L21/66 ,  H01L21/67 ,  H01L21/311

CPC classification number: H01L22/12 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L22/20

Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Abstract translation: 在等离子体蚀刻室中平坦化半导体衬底的上表面的方法包括将衬底支撑在衬底支撑组件的支撑表面上，该衬底支撑组件包括其中独立控制的热控元件的阵列，其可操作以控制空间和时间温度 的基板支撑组件的支撑表面以形成独立可控的加热器区域，其形成为对应于横跨半导体基板的上表面的期望温度分布。 在等离子体蚀刻期间跨越半导体衬底的上表面的蚀刻速率取决于其局部温度，其中确定期望的温度分布，使得半导体衬底的上表面在预定时间内被平坦化。 将衬底等离子体蚀刻预定时间，从而平坦化衬底的上表面。

公开(公告)号：US20160086795A1

公开(公告)日：2016-03-24

申请号：US14954586

申请日：2015-11-30

Applicant: Lam Research Corporation

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。 离子离子等离子体可以用于各种蚀刻工艺中。

公开(公告)号：US09230819B2

公开(公告)日：2016-01-05

申请号：US14184491

申请日：2014-02-19

Applicant: Lam Research Corporation

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/00 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。 离子离子等离子体可以用于各种蚀刻工艺中。

公开(公告)号：US20150249016A1

公开(公告)日：2015-09-03

申请号：US14337953

申请日：2014-07-22

Applicant: Lam Research Corporation

Inventor： Monica Titus ,  Gowri Kamarthy ,  Harmeet Singh ,  Yoshie Kimura ,  Meihua Shen ,  Baosuo Zhou ,  Yifeng Zhou ,  John Hoang

IPC: H01L21/3065 ,  H01L21/66 ,  H01L21/67 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L22/12 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L22/20

Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Abstract translation: 在等离子体蚀刻室中平坦化半导体衬底的上表面的方法包括将衬底支撑在衬底支撑组件的支撑表面上，该衬底支撑组件包括其中独立控制的热控元件的阵列，其可操作以控制空间和时间温度 的基板支撑组件的支撑表面以形成独立可控的加热器区域，其形成为对应于横跨半导体基板的上表面的期望温度分布。 在等离子体蚀刻期间跨越半导体衬底的上表面的蚀刻速率取决于其局部温度，其中确定期望的温度分布，使得半导体衬底的上表面在预定时间内被平坦化。 将衬底等离子体蚀刻预定时间，从而平坦化衬底的上表面。