公开(公告)号：US11581398B2

公开(公告)日：2023-02-14

申请号：US17273468

申请日：2019-09-06

申请人： LFOUNDRY S.R.L

发明人： Carsten Schmidt ,  Gerhard Spitzlsperger

IPC分类号： H01L49/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00

摘要： After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.

公开(公告)号：US10002836B2

公开(公告)日：2018-06-19

申请号：US15121419

申请日：2015-02-27

申请人： LFoundry S.r.l.

发明人： Gerhard Spitzlsperger ,  Carsten Schmidt

IPC分类号： H01L29/66 ,  H01L23/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/74 ,  H01L21/762 ,  H01L29/06 ,  H01L29/808 ,  H01L29/732 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/08 ,  H01L29/739 ,  H01L29/74

CPC分类号： H01L23/562 ,  H01L21/6835 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/43 ,  H01L27/0611 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/808 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/4502 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： A method of fabricating a semiconductor product including processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the wafer. Backside processing of the wafer includes forming implantations from the backside, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.

公开(公告)号：US12048166B2

公开(公告)日：2024-07-23

申请号：US17295529

申请日：2019-11-21

申请人： LFOUNDRY S.R.L.

发明人： Carsten Schmidt ,  Mario Blasini ,  Gerhard Spitzlsperger ,  Alessandro Montagna

IPC分类号： H10B61/00 ,  G01R33/07 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80 ,  H10N59/00

CPC分类号： H10B61/00 ,  G01R33/072 ,  G01R33/077 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H10N52/01 ,  H10N52/101 ,  H10N52/80 ,  H10N59/00

摘要： A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer.

公开(公告)号：US12119412B2

公开(公告)日：2024-10-15

申请号：US17276894

申请日：2019-09-20

申请人： LFOUNDRY S.R.L.

发明人： Carsten Schmidt ,  Gerhard Spitzlsperger

IPC分类号： H01L29/872 ,  H01L29/06

CPC分类号： H01L29/872 ,  H01L29/0619

摘要： A semiconductor vertical Schottky diode device, having: a substrate of semiconductor material, with a front surface and a back surface; a lightly doped region formed in a surface portion of the substrate facing the front surface, having a first conductivity type; a first electrode formed on the lightly doped region on the front surface of the substrate, to establish a Schottky contact; a highly doped region at the back surface of the substrate, in contact with the lightly doped region and having the first conductivity type; and a second electrode electrically in contact with the highly doped region, on the back surface of the substrate, to establish an Ohmic contact.

公开(公告)号：US20220246840A1

公开(公告)日：2022-08-04

申请号：US17625634

申请日：2020-07-08

申请人： LFOUNDRY S.R.L.

发明人： Carsten Schmidt ,  Gerhard Spitzlsperger ,  Daniel Hohnloser

IPC分类号： H01L43/06 ,  H01L43/04 ,  H01L43/14 ,  G01R33/07 ,  G01R33/00

摘要： An integrated Hall sensor is provided with: a main wafer (10) of semiconductor material having a substrate (101) with a first surface (101a) and a second surface (101b), opposite to the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1′, 2′, 3′, 4′) arranged at least one of the first and second surfaces (101a, 101b) of the substrate (101); an isolation structure (109) in the substrate (101) defining a Hall sensor plate (103) of the integrated Hall sensor, the Hall sensor terminals being arranged in the isolation structure (109). The integrated Hall sensor moreover has a test or calibration coil integrated in the wafer (10), having a plurality of windings formed, at least in part, by metal portions (130b, 170b; 130a, 170a) arranged above the first and second surfaces (101a, 101b) of the substrate (101) and defining an inner volume (1001) entirely enclosing the Hall sensor plate (103).

公开(公告)号：US20160379936A1

公开(公告)日：2016-12-29

申请号：US15121419

申请日：2015-02-27

申请人： LFOUNDRY S.R.L.

发明人： Gerhard Spitzlsperger ,  Carsten Schmidt

IPC分类号： H01L23/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L21/74 ,  H01L23/522 ,  H01L27/092 ,  H01L29/78 ,  H01L29/739 ,  H01L29/732 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/562 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823418 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/43 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/808 ,  H01L2224/4502

摘要： A method of fabricating a semiconductor product includes processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface of the wafer. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the semiconductor wafer. Backside processing of the semiconductor wafer includes forming implantations from the backside of the wafer, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.

摘要翻译： 一种制造半导体产品的方法包括从前表面处理半导体晶片，所述前表面包括设置在与所述前表面相邻的所述晶片的所述基板中的结构，并且形成嵌入在所述晶片的前表面上的电介质层中的布线。 晶片在其前表面安装到载体晶片，使得可以从晶片的背面去除材料以使半导体晶片变薄。 半导体晶片的背面处理包括从晶片的背面形成注入，形成深沟槽以将结构与晶片内的其它结构隔离，形成通硅通孔以接触晶片前侧的特征，并形成主体 联系。 可以在同一晶片内产生多个器件。