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15 条记录 (耗时 0.023 秒)

    Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)
    1.
    发明申请
    Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) 有权
    在CMOS技术中使用浅沟槽隔离（STI）来设计反向窄宽度效应（INWE）的方法，

    公开(公告)号：US20060024910A1

    公开(公告)日：2006-02-02

    申请号：US10899664

    申请日：2004-07-27

    申请人： Amitava Chatterjee ,  Alwin Tsao ,  Manuel Quevedo-Lopez ,  Jong Yoon ,  Shaoping Tang

    发明人： Amitava Chatterjee ,  Alwin Tsao ,  Manuel Quevedo-Lopez ,  Jong Yoon ,  Shaoping Tang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76237 ,  H01L21/823878

    摘要： A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).

    摘要翻译： 公开了一种形成隔离结构的方法（200），并且包括在与隔离区域相关联的半导体本体（214）中形成隔离沟槽，并用植入物掩模材料（216）填充隔离沟槽的底部。 在其底部填充有注入掩模材料之后，在隔离沟槽（218）中进行成角度的离子注入，从而在半导体本体中形成阈值电压补偿区域。 随后，隔离沟槽填充有电介质材料（220）。

    Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication
    6.
    发明申请
    Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication 有权
    用于减轻浅沟槽隔离制造的蚀刻停止限幅的方法和系统

    公开(公告)号：US20050282351A1

    公开(公告)日：2005-12-22

    申请号：US10874038

    申请日：2004-06-22

    申请人： Manuel Quevedo-Lopez ,  James Chambers ,  Leif Olsen

    发明人： Manuel Quevedo-Lopez ,  James Chambers ,  Leif Olsen

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8238

    CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878

    摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.

    摘要翻译： 本发明通过在沟槽填充操作期间保持蚀刻停止层（206）的形状和密度来促进半导体制造。 通过在沟槽填充操作之前在蚀刻停止层（206）上形成保护合金衬垫层（310）来保持蚀刻停止层（206）的形状和密度。 保护合金衬套（310）由对沟槽填充操作中使用的材料具有耐受性的合金构成。 结果，减轻了对蚀刻停止层（206）的削波和/或损伤，从而有利于采用蚀刻停止层（206）的随后的平坦化工艺。 此外，形成的保护合金（310）的厚度和组成（1706）的选择产生施加到未成形晶体管器件的沟道区域的应力量和类型（1704），最终提供了沟道迁移率的改善。

    THERMAL ANNEAL METHOD FOR A HIGH-K DIELECTRIC
    7.
    发明申请
    THERMAL ANNEAL METHOD FOR A HIGH-K DIELECTRIC 审中-公开
    用于高K电介质的热绝缘方法

    公开(公告)号：US20080242114A1

    公开(公告)日：2008-10-02

    申请号：US11695324

    申请日：2007-04-02

    申请人： Manuel Quevedo-Lopez ,  Husam Alshareef

    发明人： Manuel Quevedo-Lopez ,  Husam Alshareef

    IPC分类号： H01L21/31

    CPC分类号： H01L21/3105 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of manufacturing a semiconductor device is provided. In one embodiment, the method provides for the formation, over a substrate, of a dielectric layer having a high dielectric constant. This dielectric layer may be exposed to a nitrogen plasma after which it may be annealed in a hydrogen containing ambient.

    摘要翻译： 提供一种制造半导体器件的方法。 在一个实施例中，该方法提供了在衬底上形成具有高介电常数的电介质层。 该介电层可以暴露于氮等离子体之后，其可以在含氢环境中进行退火。

    PLASMA NITRIDED GATE OXIDE, HIGH-K METAL GATE BASED CMOS DEVICE
    8.
    发明申请
    PLASMA NITRIDED GATE OXIDE, HIGH-K METAL GATE BASED CMOS DEVICE 审中-公开
    等离子体氮化物氧化物，高K金属栅基CMOS器件

    公开(公告)号：US20080237604A1

    公开(公告)日：2008-10-02

    申请号：US11694419

    申请日：2007-03-30

    申请人： Husam Niman Alshareef ,  Manuel Quevedo-Lopez

    发明人： Husam Niman Alshareef ,  Manuel Quevedo-Lopez

    IPC分类号： H01L27/108 ,  H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3145 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： In accordance with the invention, there are CMOS devices and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate including a first active region and a second active region and a first transistor device over the first active region, wherein the first transistor device includes a high-K layer over the first active region, a first dielectric capping layer on the high-K layer, and a first metal gate layer over the first dielectric capping layer. The CMOS device can also include a second transistor device over the second active region, wherein the second transistor device includes a high-K layer over the second active region, a second dielectric capping layer on the second high-K layer, and a second metal gate layer over the second dielectric capping layer.

    摘要翻译： 根据本发明，存在CMOS器件和半导体器件及其制造方法。 CMOS器件可以包括在第一有源区上方包括第一有源区和第二有源区的衬底和第一晶体管器件，其中第一晶体管器件包括在第一有源区上的高K层，第一介电覆盖层 在高K层上，以及在第一介电覆盖层上方的第一金属栅极层。 CMOS器件还可以包括在第二有源区上的第二晶体管器件，其中第二晶体管器件包括在第二有源区上的高K层，在第二高K层上的第二介电覆盖层，以及第二金属 栅极层在第二介电覆盖层上。

    Shallow trench isolation devices and methods
    9.
    发明申请
    Shallow trench isolation devices and methods 有权
    浅沟槽隔离装置及方法

    公开(公告)号：US20080157264A1

    公开(公告)日：2008-07-03

    申请号：US11654329

    申请日：2007-01-17

    申请人： Jin Zhao ,  Manuel Quevedo-Lopez ,  Louis H. Breaux

    发明人： Jin Zhao ,  Manuel Quevedo-Lopez ,  Louis H. Breaux

    IPC分类号： H01L29/00 ,  H01L21/76

    CPC分类号： H01L21/76224 ,  H01L21/823481

    摘要： One embodiment of the present invention relates to a method of forming an isolation structure. During this method, an isolation trench is formed within a semiconductor body. After this trench is formed, it is filled by performing multiple high-frequency plasma depositions to deposit multiple dielectric layers over the semiconductor body. A first of the multiple layers is deposited at a high-frequency power of between approximately 100 watts and approximately 900 watts.

    摘要翻译： 本发明的一个实施例涉及形成隔离结构的方法。 在该方法中，在半导体本体内形成隔离沟槽。 在形成该沟槽之后，通过执行多个高频等离子体沉积来填充半导体本体上的多个电介质层。 多层中的第一层以约100瓦至约900瓦的高频功率沉积。