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    Fast and efficient circuit for identifying errors introduced in Reed-Solomon codewords
    2.
    发明授权
    Fast and efficient circuit for identifying errors introduced in Reed-Solomon codewords 失效
    快速高效的电路，用于识别Reed-Solomon码字中引入的错误

    公开(公告)号：US5384786A

    公开(公告)日：1995-01-24

    申请号：US679570

    申请日：1991-04-02

    申请人： Trent Dudley ,  Neal Glover ,  Larry King

    发明人： Trent Dudley ,  Neal Glover ,  Larry King

    IPC分类号： G06F11/10 ,  H03M13/15 ,  H03M13/00

    CPC分类号： G06F11/1076 ,  G06F11/1008 ,  H03M13/151

    摘要： Apparatus and methods are disclosed for providing an improved system for identifying the location and value of errors introduced in binary data encoded using Reed-Solomon and related codes and to detect miscorrections of such codes with an auxiliary code. The invention employs an architecture based on a microcode engine that is specialized for error identification and that supports interleaved codewords. This architecture can be efficiently fabricated as an integrated circuit, yet is capable of identifying multiple introduced errors "on the fly" i.e. with performance sufficient to not significantly slow the process of reading from data storage or transmission subsystems such as, but not limited to, optical disks. In the preferred embodiment, a new two-step method of error syndrome computation is employed to reduce circuit cost and complexity. An improved iterative algorithm is provided which reduces circuit cost and complexity and decreases the time required to generate the error locator polynomial. Cyclic redundancy check (CRC) information is adjusted as introduced errors are identified during the Chien search, thus reducing the time required to protect against ECC miscorrection. Externally-specified error thresholds allow detection of excessive numbers of errors.

    摘要翻译： 公开了用于提供改进的系统的装置和方法，该系统用于识别使用Reed-Solomon和相关代码编码的二进制数据中引入的误差的位置和值，并且用辅助码来检测这些代码的误差。 本发明采用基于专用于错误识别并支持交错码字的微代码引擎的架构。 该架构可以有效地制造为集成电路，但是能够“即时”地识别多个引入的错误，即具有足以不显着地减慢从数据存储或传输子系统读取的过程的性能，例如但不限于， 光盘。 在优选实施例中，采用新的误差校正计算的两步法来降低电路成本和复杂度。 提供了一种改进的迭代算法，其降低了电路成本和复杂性，并减少了生成误差定位多项式所需的时间。 循环冗余校验（CRC）信息被调整，因为在Chien搜索期间识别出引入的错误，从而减少了防止ECC错误修复所需的时间。 外部指定的错误阈值允许检测到过多的错误。

    Synchronous read channel employing discrete timing recovery, transition detector, and sequence detector
    4.
    发明授权
    Synchronous read channel employing discrete timing recovery, transition detector, and sequence detector 失效
    采用离散定时恢复，转换检测器和序列检测器的同步读取通道

    公开(公告)号：US5812334A

    公开(公告)日：1998-09-22

    申请号：US210302

    申请日：1994-03-16

    申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan Armstrong ,  Trent Dudley ,  Bill Foland ,  Neal Glover ,  Larry King

    发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan Armstrong ,  Trent Dudley ,  Bill Foland ,  Neal Glover ,  Larry King

    IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

    CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

    摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

    摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。 公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

    Digital pulse detector
    7.
    发明授权
    Digital pulse detector 失效
    数字脉冲检测器

    公开(公告)号：US5329554A

    公开(公告)日：1994-07-12

    申请号：US879938

    申请日：1992-05-08

    申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

    发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

    IPC分类号： G11B20/10 ,  G11B20/14 ,  H03K5/1532 ,  H03K5/19 ,  H04L25/08 ,  H04L27/00 ,  H04L27/06

    CPC分类号： G11B20/10037 ,  G11B20/10009 ,  G11B20/1403 ,  H03K5/19

    摘要： Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.

    摘要翻译： 公开了一种使用四个模拟信号样本的脉冲检测器，一旦超过脉冲信号电平峰值时间的一个采样就检测脉冲。 脉冲检测器可以通过在脉冲峰值的中心采样或通过在脉冲峰值的任一侧进行采样来检测脉冲。 脉冲检测器在跟踪数据的同时检测脉冲，并且在采集具有已知数据模式的信号的定时和增益锁定的同时使用用于检测脉冲的替代检测系统。 检测器使用采样信号电平或两个采样的移动平均值进行检测。

    Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency
    8.
    发明授权
    Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency 失效
    采用频率合成器的同步读通道，用于将定时恢复锁相环锁定到参考频率

    公开(公告)号：US5917668A

    公开(公告)日：1999-06-29

    申请号：US822174

    申请日：1997-03-21

    申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

    发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

    IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

    CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

    摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.

    摘要翻译： 公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 为了在进入定时恢复采集模式时确保小的频率误差，定时恢复锁相环（PLL）首先被锁定到与写入频率相同的标称读取频率。 这是通过将写入频率合成器的输出以锁定参考模式复用到定时恢复PLL来实现的。 此后，来自读取头的模拟信号被多路复用到定时恢复PLL中，以便获取在用户数据之前记录的获取前导码的实际频率和相位。

    Reed-Solomon code system employing k-bit serial techniques for encoding and burst error trapping
    9.
    发明授权
    Reed-Solomon code system employing k-bit serial techniques for encoding and burst error trapping 失效
    Reed-Solomon码系统采用k位串行技术进行编码和突发错误捕获

    公开(公告)号：US5875200A

    公开(公告)日：1999-02-23

    申请号：US832614

    申请日：1997-03-28

    申请人： Neal Glover ,  Trent Dudley

    发明人： Neal Glover ,  Trent Dudley

    IPC分类号： G11B20/18 ,  H03M13/15 ,  H03M13/17 ,  H03M13/00 ,  H03M13/22

    CPC分类号： H03M13/151 ,  G11B20/1833 ,  H03M13/17

    摘要： Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite-field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.

    摘要翻译： 公开了用于提供用于对Reed-Solomon和相关代码进行编码和解码的改进系统的装置和方法。 该系统采用k位串行移位寄存器进行编码和残差生成。 对于解码，在读取数据时产生残差。 单脉冲串错误通过对该残余物进行操作的k位串行突发捕获解码器实时校正。 使用非实时固件解码器校正大于单个突发的错误情况，该解码器检索残差并将其转换为余数，然后将余数转换为综合征，然后尝试计算来自综合征的错误位置和值。 在优选实施例中，在突发捕获电路内采用新的低阶第一，k位串行有限域常数乘法器。 此外，支持不需要等于信息字节大小的代码符号大小。 所公开的方法的实现者可以选择用于多脉冲串校正的时间效率或空间有效的固件。