公开(公告)号：US06724594B2

公开(公告)日：2004-04-20

申请号：US09742037

申请日：2000-12-20

申请人： Laurence D. Lewicki ,  Manoj N. Rana ,  Arlo Aude

发明人： Laurence D. Lewicki ,  Manoj N. Rana ,  Arlo Aude

IPC分类号： H02H320

CPC分类号： G01R31/318572 ,  H02H9/048

摘要： There is disclosed a test multiplexer having over voltage protection for use in integrated circuitry, along with methods of operating the same. An exemplary test multiplexer according to one embodiment of the present invention includes a plurality of MOSFET devices and over voltage protection circuitry. The plurality of MOSFET devices, including both p-type and n-type MOSFET devices, cooperate to pass an input signal to an output signal line of the test multiplexer while the test multiplexer is enabled. The over voltage protection circuitry is biased so that a difference between the input signal voltage and a bias voltage does not exceed breakdown when the test multiplexer is disabled. An important aspect hereof is that the test multiplexer is compliant to input voltages that exceed the positive supply rail, and is capable of sustaining a high or otherwise out of threshold single ended voltage at the input without latching up.

摘要翻译： 公开了一种具有用于集成电路中的过电压保护的测试多路复用器及其操作方法。 根据本发明的一个实施例的示例性测试多路复用器包括多个MOSFET器件和过电压保护电路。 包括p型和n型MOSFET器件的多个MOSFET器件在测试复用器被使能的同时，将输入信号传送到测试多路复用器的输出信号线。 过电压保护电路被偏置，使得当测试复用器被禁用时，输入信号电压和偏置电压之间的差异不会超过击穿。 这里的一个重要方面是测试多路复用器符合超过正电源轨的输入电压，并且能够在输入端保持高电平或以其他方式超出阈值单端电压而不锁存。

公开(公告)号：US06930537B1

公开(公告)日：2005-08-16

申请号：US10061939

申请日：2002-02-01

申请人： Vijaya G. Ceekala ,  James B. Wieser ,  Devnath Varadarajan ,  Laurence D. Lewicki ,  Jitendra Mohan

发明人： Vijaya G. Ceekala ,  James B. Wieser ,  Devnath Varadarajan ,  Laurence D. Lewicki ,  Jitendra Mohan

IPC分类号： G05F1/10 ,  G05F3/02 ,  G05F3/30

CPC分类号： G05F3/30

摘要： A band-gap reference circuit with averaged current mirror offsets is provided that includes a differential amplifier circuit, a low current transistor circuit, a high current transistor circuit, and a configuration circuit. The differential amplifier circuit includes a first input node operable to receive a first input signal, a second input node operable to receive a second input signal, and an output node operable to generate an output signal based on the input signal difference. The low current transistor circuit is coupled to the differential amplifier circuit and is operable to receive the output signal and to generate the first input signal based on the output signal. The high current transistor circuit is coupled to the differential amplifier circuit and is operable to receive the output signal and to generate the second input signal based on the output signal. The configuration circuit is coupled to the low current transistor circuit and to the high current transistor circuit. The configuration circuit is operable to configure the band-gap reference circuit for a plurality of states by switching a plurality of components between the low current transistor circuit and the high current transistor circuit at specified intervals.

摘要翻译： 提供了具有平均电流镜偏移的带隙参考电路，其包括差分放大器电路，低电流晶体管电路，高电流晶体管电路和配置电路。 差分放大器电路包括可操作以接收第一输入信号的第一输入节点，可操作以接收第二输入信号的第二输入节点和可用于基于输入信号差产生输出信号的输出节点。 低电流晶体管电路耦合到差分放大器电路，并且可操作以接收输出信号并且基于输出信号产生第一输入信号。 高电流晶体管电路耦合到差分放大器电路并且可操作以接收输出信号并且基于输出信号产生第二输入信号。 配置电路耦合到低电流晶体管电路和高电流晶体管电路。 配置电路可操作以通过以指定的间隔切换低电流晶体管电路和高电流晶体管电路之间的多个分量来配置多个状态的带隙基准电路。

公开(公告)号：US6060912A

公开(公告)日：2000-05-09

申请号：US933781

申请日：1997-09-19

申请人： Ion E. Opris ,  Laurence D. Lewicki

发明人： Ion E. Opris ,  Laurence D. Lewicki

IPC分类号： H03K3/356 ,  G11C7/06

CPC分类号： H03K3/35613 ,  H03M1/0872 ,  H03M1/38

摘要： A strobed comparator circuit with reduced signal propagation time has a regenerative latch in which, during the reset phase of operation, its output nodes are discharged to a common potential which is close to the regenerative voltage level of the cross-coupled transistors forming such regenerative latch rather than to circuit ground. Accordingly, overall signal propagation time is reduced by the amount of reduction in charging time necessary for one of the discharged nodes to recharge above the threshold voltage of one of the cross-coupled latch transistors. Also included is an output monitoring circuit which determines whether the regenerative latch has remained in a metastable state.

摘要翻译： 具有减小的信号传播时间的选通比较器电路具有再生锁存器，其中在复位操作阶段期间，其输出节点被放电到接近形成这种再生锁存器的交叉耦合晶体管的再生电压电平的公共电位 而不是电路接地。 因此，整个信号传播时间减少了放电节点之一所需的充电时间的减少量超过交叉耦合的锁存晶体管中的一个的阈值电压。 还包括输出监视电路，其确定再生锁存器是否保持在亚稳态。

公开(公告)号：US07571360B1

公开(公告)日：2009-08-04

申请号：US10973843

申请日：2004-10-26

申请人： Laurence D. Lewicki ,  Amjad T. Obeidat ,  Nicolas Nodenot

发明人： Laurence D. Lewicki ,  Amjad T. Obeidat ,  Nicolas Nodenot

IPC分类号： G06F11/00

CPC分类号： G06F11/2215

摘要： A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a bit period to create errors at a relatively high bit error rate. This is accomplished by intentionally introducing an interpolator offset in a phase position of a data clock signal. The test control unit generates a first bit error rate and then subsequently generates a second bit error rate. The test control unit then uses the values of the first and second bit error rates to extrapolate a value of bit error rate for the clock and data recovery circuit that corresponds to a zero value of interpolator offset.

摘要翻译： 公开了一种提供具有快速误码率自检能力的时钟和数据恢复电路的系统和方法。 提供了一个误码率测试控制单元，使得时钟和数据恢复电路对位周期边缘附近的数据采样，以相对较高的误码率产生错误。 这是通过有意地在数据时钟信号的相位位置引入内插器偏移来实现的。 测试控制单元产生第一误码率，然后产生第二误码率。 测试控制单元然后使用第一和第二位错误率的值来推断对应于内插器偏移的零值的时钟和数据恢复电路的误码率值。

公开(公告)号：US07555091B1

公开(公告)日：2009-06-30

申请号：US10973131

申请日：2004-10-26

申请人： Laurence D. Lewicki ,  Amjad T. Obeidat ,  Nicolas Nodenot

发明人： Laurence D. Lewicki ,  Amjad T. Obeidat ,  Nicolas Nodenot

IPC分类号： H03D3/24

CPC分类号： H04L7/0079 ,  G01R31/31715 ,  G01R31/31726 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L1/24 ,  H04L7/0025 ,  H04L7/033

摘要： A system and method is disclosed for providing a clock and data recovery circuit with a self test capability. A test control unit is provided that causes the clock and data recovery circuit to continuously alter a phase of an interpolated clock signal. A user selects a preselected bit pattern that causes the digital control circuitry of the clock and data recovery circuit to advance or retard the phase of the interpolated clock signal. The test control unit compares the advanced or retarded phase of the interpolated clock signal with a reference clock signal to determine a frequency difference between the two clock signals. The test control unit uses the frequency difference to determine the test status of the clock and data recovery circuit.

摘要翻译： 公开了一种用于提供具有自检能力的时钟和数据恢复电路的系统和方法。 提供了一种使时钟和数据恢复电路连续地改变内插时钟信号的相位的测试控制单元。 用户选择使得时钟和数据恢复电路的数字控制电路推进或延迟内插时钟信号的相位的预选位模式。 测试控制单元将内插时钟信号的高级或延迟相位与参考时钟信号进行比较，以确定两个时钟信号之间的频率差。 测试控制单元使用频率差来确定时钟和数据恢复电路的测试状态。

公开(公告)号：US06486821B1

公开(公告)日：2002-11-26

申请号：US09911331

申请日：2001-07-23

申请人： Arlo J. Aude ,  Laurence D. Lewicki ,  Jitendra Mohan

发明人： Arlo J. Aude ,  Laurence D. Lewicki ,  Jitendra Mohan

IPC分类号： H03M112

CPC分类号： H03F1/086

摘要： There is disclosed an amplifier for operating from a power supply having a first voltage level. The amplifier comprises: 1) a plurality of thick-oxide field effect transistors, each of the plurality of thick-oxide field effect transistors having a relatively thick oxide layer and fabricated using a first process such that the each thick-oxide field effect transistor can withstand a gate-to-source difference, a gate-to-drain difference, and a gate-to-bulk difference at least equal to a first maximum operating voltage, wherein the first. maximum operating voltage is at least equal to the first voltage level; and 2) a first thin-oxide field effect transistor coupled to a first input of the amplifier, the first thin-oxide field effect transistor having a relatively thin oxide layer and fabricated using a second process such that the first thin-oxide field effect transistor can withstand a gate-to-source difference, a gate-to-drain difference, and a gate-to-bulk difference at least equal to a second maximum operating voltage, wherein the second maximum operating voltage is less than the first voltage level.

摘要翻译： 公开了一种用于从具有第一电压电平的电源操作的放大器。 放大器包括：1）多个厚氧化物场效应晶体管，多个厚氧化物场效应晶体管中的每一个具有相对较厚的氧化物层，并且使用第一工艺制造，使得每个厚氧化物场效应晶体管可以 承受栅极至源极的差异，栅极至漏极差异以及至少等于第一最大工作电压的栅极与体积之差，其中第一。 最大工作电压至少等于第一电压电平; 以及2）耦合到所述放大器的第一输入的第一薄氧化物场效应晶体管，所述第一薄氧化物场效应晶体管具有相对薄的氧化物层，并且使用第二工艺制造，使得所述第一薄氧化物场效应晶体管 可以承受栅极至源极的差异，栅极至漏极差异以及至少等于第二最大工作电压的栅极至体积差异，其中第二最大工作电压小于第一电压电平。

公开(公告)号：US5963156A

公开(公告)日：1999-10-05

申请号：US955896

申请日：1997-10-22

申请人： Laurence D. Lewicki ,  Ion E. Opris

发明人： Laurence D. Lewicki ,  Ion E. Opris

IPC分类号： G11C27/02 ,  H03F1/30 ,  H03F3/45 ,  H03M3/02

CPC分类号： H03F3/45986 ,  G11C27/026 ,  H03F1/303 ,  H03F3/45188 ,  H03F3/4521 ,  H03F3/45959 ,  H03F3/45995

摘要： A sample and hold (S/H) circuit with common mode differential signal feedback for converting single-ended signals to differential signals includes a feedback loop for the input switched capacitor circuit to ensure that the input common mode voltage for the differential amplifier is maintained at a known value during the hold phase of operation. The feedback loop consists of a three-input error amplifier which monitors the two voltages at the differential input terminals of the differential amplifier in relation to the common mode reference voltage and generates a feedback voltage which is applied to the input terminals of the input switched capacitor circuit during the hold phase of operation. If both of the differential input terminal voltages are either more negative or more positive than the common mode reference voltage then the feedback voltage generated by the error amplifier is made more positive or negative, respectively.

摘要翻译： 具有用于将单端信号转换为差分信号的共模差分信号反馈的采样和保持（S / H）电路包括用于输入开关电容器电路的反馈回路，以确保差分放大器的输入共模电压保持在 在操作的保持阶段的已知值。 反馈回路包括一个三输入误差放大器，它相对于共模参考电压来监视差分放大器差分输入端的两个电压，并产生一个反馈电压，该反馈电压被施加到输入开关电容器的输入端 电路在运行的保持阶段。 如果差分输入端子电压两者都比共模参考电压更负或更正，则误差放大器产生的反馈电压分别变为正或负。

公开(公告)号：US5847607A

公开(公告)日：1998-12-08

申请号：US772011

申请日：1996-12-19

申请人： Laurence D. Lewicki ,  Ion E. Opris

发明人： Laurence D. Lewicki ,  Ion E. Opris

IPC分类号： H03F3/45 ,  H03F1/14

CPC分类号： H03F3/45802 ,  H03F3/45188 ,  H03F3/45286 ,  H03F3/4565 ,  H03F3/45654 ,  H03F3/45798 ,  H03F2203/45421 ,  H03F2203/45508 ,  H03F2203/45651

摘要： A high speed fully differential operational amplifier with fast settling time for switched capacitor applications includes a high gain active cascode applied to the operational amplifier's input stage transistors to improve the gain, provide a higher output impedance, and thus, reduce the Miller feedback gate drain capacitance of the input stage devices. This improves the speed of the amplifier. A biasing technique is used to keep the active cascodes biased during transient overload so that settling will not be adversely affected during the recovery of the cascodes. A pair of transistors are used to feed forward a fraction of the tail current to "keep-alive" the cascode transistors. In other words, the fraction of the tail current that is fed to the source of the cascode transistors via the keep-alive transistors effectively biases the active cascodes sufficiently so that they do not turn off completely during slewing.

摘要翻译： 具有快速建立时间的开关电容应用的高速全差分运算放大器包括一个高增益有源共源共栅，用于运算放大器的输入级晶体管，以提高增益，提供更高的输出阻抗，从而降低了米勒反馈栅极漏极电容 的输入级装置。 这提高了放大器的速度。 偏置技术用于在瞬态过载期间保持有源共源共轭偏置，从而在级联恢复期间沉降不会受到不利影响。 一对晶体管用于馈送一部分尾电流以“保持”共源共栅晶体管。 换句话说，通过保持活体晶体管馈送到共源共栅晶体管的源极的尾部电流的分数有效地有效地偏压有源级联，使得它们在回转期间不会完全关断。

公开(公告)号：US07187212B1

公开(公告)日：2007-03-06

申请号：US10973220

申请日：2004-10-26

申请人： Alan E. Segervall ,  Laurence D. Lewicki

发明人： Alan E. Segervall ,  Laurence D. Lewicki

IPC分类号： H03K19/20 ,  H03K19/086 ,  H03K19/094 ,  H03K19/003

CPC分类号： H03K19/0016

摘要： A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle “power down” state to an active “power up” state in current mode logic (CML) transmitter output circuits. The invention comprises a capacitor coupled to a bias transistor and a charge switch circuit for controlling the operation of the capacitor. The capacitor has a value of capacitance that is equal in magnitude and opposite in sign to the Miller coupling capacitance in the bias transistor. The capacitor compensates for the Miller coupling capacitance within the bias transistor in less than ten nanoseconds. This permits a CML transmitter to more quickly restart the transmission of data after an active state has been initiated.

摘要翻译： 公开了一种用于提供快速开启偏置电路的系统和方法，其允许在当前模式逻辑（CML）发射机输出电路中从空闲“掉电”状态到主动“上电”状态的快速转变。 本发明包括耦合到偏置晶体管的电容器和用于控制电容器的操作的充电开关电路。 电容器的电容值与偏置晶体管中的米勒耦合电容的幅度相等，符号相反。 电容器补偿偏置晶体管内的Miller耦合电容小于10纳秒。 这允许CML发射机在激活状态被启动之后更快地重启数据传输。

公开(公告)号：US06859387B1

公开(公告)日：2005-02-22

申请号：US09569954

申请日：2000-05-12

申请人： Arlo J. Aude ,  Laurence D. Lewicki

发明人： Arlo J. Aude ,  Laurence D. Lewicki

IPC分类号： G06F7/48 ,  H03M1/06 ,  H03M1/12 ,  H03M1/38 ,  H03M1/44

CPC分类号： G06F7/4824 ,  H03M1/0695 ,  H03M1/44

摘要： Three-state binary adders are disclosed for use in pipelined analog-to-digital converters. According to one advantageous embodiment, a three-state binary adder is provided for use in a digital signal processing system. The three-state binary adder is operable to generate binary codes consisting of three states, namely, “00”, “01” and “10.”

摘要翻译： 公开了用于流水线模数转换器的三态二进制加法器。 根据一个有利的实施例，提供一种用于数字信号处理系统中的三态二进制加法器。 三态二进制加法器可操作以产生由三个状态组成的二进制码，即“00”，“01”和“10”。