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14 条记录 (耗时 0.04 秒)

    Fabrication of trench capacitors using disposable hard mask
    5.
    发明授权
    Fabrication of trench capacitors using disposable hard mask 失效
    使用一次性硬掩模制作沟槽电容器

    公开(公告)号：US06190955B1

    公开(公告)日：2001-02-20

    申请号：US09014433

    申请日：1998-01-27

    申请人： Matthias Ilg ,  Richard L. Kleinhenz ,  Soichi Nadahara ,  Ronald W. Nunes ,  Klaus Penner ,  Klaus Roithner ,  Radhika Srinivasan ,  Shigeki Sugimoto

    发明人： Matthias Ilg ,  Richard L. Kleinhenz ,  Soichi Nadahara ,  Ronald W. Nunes ,  Klaus Penner ,  Klaus Roithner ,  Radhika Srinivasan ,  Shigeki Sugimoto

    IPC分类号： H01L218244

    CPC分类号： H01L21/3081

    摘要： Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer. The methods are especially useful for forming deep trenches in silicon substrates with pad dielectric layers.

    摘要翻译： 使用BSG的半导体衬底的改进的沟槽形成方法避免了与常规TEOS硬掩模技术相关的问题。 所述方法包括：（a）提供半导体衬底，（b）在衬底上施加保形层硼硅酸盐玻璃（BSG）;（c）在BSG层上形成图案化的光刻胶层，由此在光刻胶下面的一部分层 （d）通过位于光致抗蚀剂层和半导体衬底之间的任何其它层，通过底层的暴露部分进行各向异性蚀刻，并进入半导体衬底，由此在半导体衬底中形成沟槽。优选地，一个 或更多的介电层在施加BSG层之前存在于衬底表面上。 可以在BSG层和光致抗蚀剂层之间的BSG层上施加一个或多个化学屏障和/或有机抗反射涂层。 该方法对于在具有焊盘电介质层的硅衬底中形成深沟槽特别有用。

    Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications
    7.
    发明授权
    Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications 有权
    浅沟槽隔离（STI），双层氧化物氮化物用于VLSI应用

    公开(公告)号：US6140208A

    公开(公告)日：2000-10-31

    申请号：US245958

    申请日：1999-02-05

    申请人： Farid Agahi ,  Gary Bronner ,  Bertrand Flietner ,  Erwin Hammerl ,  Herbert Ho ,  Radhika Srinivasan

    发明人： Farid Agahi ,  Gary Bronner ,  Bertrand Flietner ,  Erwin Hammerl ,  Herbert Ho ,  Radhika Srinivasan

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76224

    摘要： A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.

    摘要翻译： 公开了浅沟槽隔离通孔的寄生泄漏的减少，其中通过在沉积氮化硅衬垫之前沉积绝缘氧化物层来增加氮化硅衬垫和有源硅侧壁之间的距离。 优选地，绝缘氧化物层包括原硅酸四乙酯。 该方法包括将一个或多个浅沟槽隔离件蚀刻成半导体晶片; 将绝缘氧化物层沉积到沟槽中; 在沟槽中生长热氧化物; 以及在沟槽中沉积氮化硅衬垫。 热氧化物可以在沉积绝缘氧化物层之前或之后生长。

    Method for forming electrical isolation for semiconductor devices
    8.
    发明授权
    Method for forming electrical isolation for semiconductor devices 失效
    用于形成半导体器件的电隔离的方法

    公开(公告)号：US6074903A

    公开(公告)日：2000-06-13

    申请号：US98203

    申请日：1998-06-16

    申请人： Rajesh Rengarajan ,  Hirofumi Inoue ,  Radhika Srinivasan ,  Jochen Beintner

    发明人： Rajesh Rengarajan ,  Hirofumi Inoue ,  Radhika Srinivasan ,  Jochen Beintner

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L21/8238

    CPC分类号： H01L21/76237

    摘要： A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.

    摘要翻译： 一种用于在硅体中形成电绝缘的半导体器件的方法。 在身体的选定区域中形成沟槽。 阻挡材料沉积在沟槽的侧壁上。 阻挡材料的一部分从沟槽的第一侧壁部分被去除以暴露沟槽的这种第一侧壁部分，同时将这种阻挡材料的一部分留在沟槽的第二侧壁部分上以在其上形成阻挡层。 电介质材料沉积在沟槽中，介电材料的一部分沉积在暴露的沟槽的第一侧壁部分上，另一部分沉积的介电材料沉积在阻挡材料上。 电介质材料在氧化环境中退火以致密化这种淀积的介电材料，阻挡层阻止沟槽的所述第二侧壁部分的氧化。 在硅体中形成多个半导体器件，这些器件通过沟槽中的电介质材料电隔离。