公开(公告)号：US20070158730A1

公开(公告)日：2007-07-12

申请号：US11328779

申请日：2006-01-10

Applicant: James Burnett ,  Leo Mathew ,  Byoung Min

Inventor： James Burnett ,  Leo Mathew ,  Byoung Min

IPC: H01L29/76

CPC classification number: H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

Abstract translation: 集成电路包括逻辑电路和存储单元。 逻辑电路包括P沟道晶体管，并且存储单元包括P沟道晶体管。 逻辑电路的P沟道晶体管包括沟道区。 沟道区具有位于具有（110）表面取向的半导体结构的侧壁的部分。 位于沿着侧壁的通道区域的部分具有第一垂直尺寸，其大于沿着具有表面的半导体结构的侧壁的存储单元的P沟道晶体管的沟道区的任何部分的垂直尺寸 （110）的方向。

公开(公告)号：US20070161171A1

公开(公告)日：2007-07-12

申请号：US11328668

申请日：2006-01-10

Applicant: James Burnett ,  Leo Mathew ,  Byoung Min

Inventor： James Burnett ,  Leo Mathew ,  Byoung Min

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

Abstract translation: 用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。 根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。 根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

公开(公告)号：US20050020015A1

公开(公告)日：2005-01-27

申请号：US10624398

申请日：2003-07-22

Applicant: Leo Mathew ,  Byoung Min

Inventor： Leo Mathew ,  Byoung Min

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/8236

CPC classification number: H01L29/785 ,  H01L21/823437 ,  H01L27/1203

Abstract: A method for creating a vertical double-gate transistor design includes providing a planar transistor layout (10) having a gate layer (12) overlying an active layer (14). In one embodiment, a first intermediate layer (18) is defined based on an overlapping region of the gate and active layers, and, using the first intermediate layer, a second intermediate layer (22) is defined which defines a spacing between at least two fins of the vertical double-gate transistor design. The second intermediate layer may also define a length and a width of the at least two fins. One embodiment modifies a dimension of the first intermediate layer prior to defining the second intermediate layer. The method further includes defining a resulting layer (24) based on a non-overlapping region of the second intermediate layer and the active layer. The resulting layer may then be used to create a mask and a semiconductor device (30) corresponding to the vertical double-gate transistor design.

Abstract translation: 一种用于产生垂直双栅极晶体管设计的方法包括提供具有覆盖有源层（14）的栅极层（12）的平面晶体管布局（10）。 在一个实施例中，基于栅极和有源层的重叠区域限定第一中间层（18），并且使用第一中间层限定第二中间层（22），其限定了至少两个 翅片垂直双栅极晶体管设计。 第二中间层还可以限定至少两个翅片的长度和宽度。 一个实施例在限定第二中间层之前修改第一中间层的尺寸。 该方法还包括基于第二中间层和有源层的非重叠区域来限定所得层（24）。 所得到的层然后可用于产生对应于垂直双栅极晶体管设计的掩模和半导体器件（30）。

公开(公告)号：US20070093054A1

公开(公告)日：2007-04-26

申请号：US11257972

申请日：2005-10-25

Applicant: Byoung Min ,  James Burnett ,  Leo Mathew

Inventor： Byoung Min ,  James Burnett ,  Leo Mathew

IPC: H01L21/4763 ,  H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成具有在垂直有源区两侧延伸的垂直有源区和水平有源区的第一晶体管。 该方法还包括形成具有垂直有源区的第二晶体管。 该方法还包括形成具有垂直有源区和仅在垂直有源区的一侧上延伸的水平有源区的第三晶体管。

公开(公告)号：US08043888B2

公开(公告)日：2011-10-25

申请号：US12016733

申请日：2008-01-18

Applicant: Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

Inventor： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

IPC: H01L21/44

CPC classification number: H01L45/1675 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

Abstract: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

Abstract translation: 形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。 形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。 当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。 当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

公开(公告)号：US20100227475A1

公开(公告)日：2010-09-09

申请号：US12784984

申请日：2010-05-21

Applicant: Leo Mathew ,  Dharmesh Jawarani

Inventor： Leo Mathew ,  Dharmesh Jawarani

IPC: H01L21/44

CPC classification number: H01L21/26506 ,  H01L31/022425 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/0312 ,  H01L31/03682 ,  H01L31/03762 ,  H01L31/03765 ,  H01L31/068 ,  H01L31/1864 ,  H01L31/1892 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material. The method can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating a semiconductor layer and the metallic layer from the substrate, wherein the semiconductor layer is a portion of the substrate. In a particular embodiment, the separation-enhancing species can be incorporated into a metallic layer and moved into the substrate, and in particular embodiment, the separation-enhancing species can be implanted into the substrate. In still another embodiment, both the techniques can be used. In a further embodiment, a dual-sided process can be performed.

Abstract translation: 形成电子器件的方法可以包括通过电化学工艺在包括半导体材料的衬底的侧面上形成金属层。 该方法还可以包括在距离侧面一定距离处将分离增强物质引入衬底中，并且将半导体层和金属层与衬底分离，其中半导体层是衬底的一部分。 在一个具体的实施方案中，分离增强物质可以结合到金属层中并移动到基底中，并且在具体实施方案中，可以将分离增强物质注入到基底中。 在另一个实施例中，可以使用这两种技术。 在另一实施例中，可以执行双面处理。

公开(公告)号：US07709303B2

公开(公告)日：2010-05-04

申请号：US11328668

申请日：2006-01-10

Applicant: James D. Burnett ,  Leo Mathew ,  Byoung W. Min

Inventor： James D. Burnett ,  Leo Mathew ,  Byoung W. Min

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

Abstract translation: 用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。 根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。 根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

公开(公告)号：US07432122B2

公开(公告)日：2008-10-07

申请号：US11327686

申请日：2006-01-06

Applicant: Leo Mathew ,  Michael G. Khazhinsky

Inventor： Leo Mathew ,  Michael G. Khazhinsky

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/20 ,  H01L21/36

CPC classification number: H01L27/0811 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/7391 ,  H01L29/785

Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Abstract translation: 电子设备可以包括门控二极管，其中门控二极管包括包括结的结二极管结构。 与结点隔开并相邻的第一导电构件可连接到第一信号线。 与结点间隔开并与其相邻的第二导电构件可以电连接到第二信号线并与第一导电构件电绝缘。 结二极管结构可以包括p-n或p-i-n结。 还描述了用于形成电子设备的过程。

公开(公告)号：US07301741B2

公开(公告)日：2007-11-27

申请号：US11130873

申请日：2005-05-17

Applicant: Michael G. Khazhinsky ,  Leo Mathew

Inventor： Michael G. Khazhinsky ,  Leo Mathew

IPC: H02H3/22

CPC classification number: H01L27/0251 ,  H01L27/0292 ,  H01L29/7855

Abstract: A rail clamp circuit (100) includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) (128), and an ESD event detector circuit (138). The MIGFET (128) has a source/drain path coupled between the first (112) and second (114) power supply voltage rails, and first and second gates. The ESD event detector circuit (138) is coupled between the first (112) and second (114) power supply voltage rails, and has first and second output terminals respectively coupled to the first and second gates of the MIGFET. In response to an electrostatic discharge (ESD) event between the first (112) and second (114) power supply voltage rails, the ESD event detector circuit (138) provides a voltage to the second gate to lower an absolute threshold voltage of the MIGFET (128) while providing a voltage to the first gate above the absolute threshold voltage so lowered, thereby making the MIGFET (128) conductive with relatively high conductivity.

Abstract translation: 轨道钳位电路（100）包括第一和第二电源电压轨道，多个独立的栅极场效应晶体管（MIGFET）（128）和ESD事件检测器电路（138）。 MIGFET（128）具有耦合在第一（112）和第二（114）电源电压轨道之间的源极/漏极路径，以及第一和第二栅极。 ESD事件检测器电路（138）耦合在第一（112）和第二（114）电源电压轨道之间，并且具有分别耦合到MIGFET的第一和第二栅极的第一和第二输出端子。 响应于第一（112）和第二（114）电源电压轨道之间的静电放电（ESD）事件，ESD事件检测器电路（138）向第二栅极提供电压以降低MIGFET的绝对阈值电压 （128），同时向第一栅极提供高于绝对阈值电压的电压，从而使MIGFET（128）具有较高导电性的导电性。

公开(公告)号：US20070181946A1

公开(公告)日：2007-08-09

申请号：US11349875

申请日：2006-02-08

Applicant: Leo Mathew ,  Lixin Ge ,  Surya Veeraraghavan

Inventor： Leo Mathew ,  Lixin Ge ,  Surya Veeraraghavan

IPC: H01L27/12

CPC classification number: H01L29/78615 ,  H01L29/785

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract translation: 一种用于制造半导体器件的方法包括图案化覆盖在绝缘体层上的半导体层，以产生第一有源区和第二有源区，其中第一有源区具有与第二有源区不同的高度，并且其中至少 所述第一有源区的一部分具有第一导电类型，并且所述第二有源区的至少一部分具有与所述半导体器件的至少沟道区中的所述第一导电类型不同的第二导电类型。 该方法还包括在第一有源区和第二有源区的至少一部分上形成栅极结构。 该方法还包括去除半导体器件的一侧上的第二有源区的一部分。