公开(公告)号：US06424044B1

公开(公告)日：2002-07-23

申请号：US10050697

申请日：2002-01-18

申请人： Licheng M. Han ,  Xu Yi ,  Joseph Zhifeng Xie ,  Mei Sheng Zhou ,  Simon Chooi

发明人： Licheng M. Han ,  Xu Yi ,  Joseph Zhifeng Xie ,  Mei Sheng Zhou ,  Simon Chooi

IPC分类号： H01L2348

CPC分类号： H01L21/76834 ,  H01L21/76807 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

摘要翻译： 公开了一种形成用作铜双镶嵌结构中的屏障和蚀刻停止层的碳化硼层的方法，以及结构本身。 除了提供对铜扩散的良好屏障之外，良好的绝缘性能，相对于介电绝缘体的高蚀刻选择性，由于其低介电常数小于5，碳化硼也提供良好的电特性。无定形碳化硼形成于 通过在约400℃的沉积温度下引入诸如B 2 H 6，B 5 H 9+的硼源气体和诸如CH 4和C 2 H 6的碳源气体的PECVD室。钝化，蚀刻停止，盖层的任何一种或任何组合 镶嵌结构可以包括碳化硼。

公开(公告)号：US06352921B1

公开(公告)日：2002-03-05

申请号：US09619377

申请日：2000-07-19

申请人： Licheng M. Han ,  Yi Xu ,  Joseph Zhifeng Xie ,  Mei Sheng Zhou ,  Simon Chooi

发明人： Licheng M. Han ,  Yi Xu ,  Joseph Zhifeng Xie ,  Mei Sheng Zhou ,  Simon Chooi

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/76807 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

公开(公告)号：US06429129B1

公开(公告)日：2002-08-06

申请号：US09594415

申请日：2000-06-16

申请人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

发明人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

公开(公告)号：US06730591B2

公开(公告)日：2004-05-04

申请号：US10186532

申请日：2002-07-01

申请人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

发明人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

摘要翻译： 一种在半导体器件中形成互连结构的方法，包括以下步骤。 提供半导体结构。 在第一实施例中，在半导体结构上形成至少一条金属线。 在金属线和半导体结构之上形成富含碳的碳化物阻挡层。 最后，在富含硅的碳化物层上形成可被氟化的介电层。 在第二实施例中，在半导体结构上形成至少一个可被氟化的氟化介电层。 图案化电介质层以在其中形成开口。 在开口内形成富含碳的碳化物阻挡层。 在结构上沉积金属化层，填充富含硅的碳化物阻挡层衬里的开口。 最后，金属化层可以被平坦化以在富含硅的碳化物阻挡层衬里的开口内形成平坦化的金属结构。

公开(公告)号：US06340608B1

公开(公告)日：2002-01-22

申请号：US09612564

申请日：2000-07-07

申请人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Ho ,  Xu Yi

发明人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Ho ,  Xu Yi

IPC分类号： H01L2150

CPC分类号： H01L24/81 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.

摘要翻译： 提供了具有暴露的金属端接垫的半导体芯片，以及具有其上相应的暴露的金属轨道的单独的基板。 在暴露的金属端接垫上方形成金属凸块。 在金属凸块上形成感光树脂插头。 半导体芯片的金属凸块与分离的基板上的对应金属轨迹对准。 金属凸块上的感光树脂插头与相应的金属轨道配合。 感光树脂插头暴露于紫外线光以固化光敏树脂插头，将半导体芯片的金属凸块永久地连接到单独基板的相应金属轨道上。

公开(公告)号：US06261942B1

公开(公告)日：2001-07-17

申请号：US09490156

申请日：2000-01-24

申请人： Mei Sheng Zhou ,  Simon Chooi ,  Xu Yi

发明人： Mei Sheng Zhou ,  Simon Chooi ,  Xu Yi

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  H01L21/312 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for introducing air into the gaps between neighboring conducting structures in a microelectronics fabrication in order to reduce the capacitative coupling between them. A patterned metal layer is deposited on a substrate. The layer is lined with a CVD-oxide. A disposable gap-filling material is deposited over the lined metal layer. A two layer “air-bridge” is formed over the gap-fill by depositing a layer of TiN over a layer of CVD-oxide. This structure is rendered porous by several chemical processes. An oxygen plasma is passed through the porous air-bridge to react with and dissolve the gap-fill beneath it. The reaction products escape through the porous air-bridge resulting in air-filled gaps.

摘要翻译： 一种在微电子制造中将空气引入相邻导电结构之间的间隙中以减少它们之间的电容耦合的方法。 图案化的金属层沉积在基底上。 该层衬有CVD氧化物。 一次性间隙填充材料沉积在衬里的金属层上。 通过在CVD氧化物层上沉积TiN层，在间隙填充上形成两层“空气桥”。 这种结构通过几种化学方法使其多孔化。 氧气等离子体通过多孔空气桥与其下方的间隙填充反应并溶解。 反应产物通过多孔气桥逸出，导致空气填充的间隙。

公开(公告)号：US07060613B2

公开(公告)日：2006-06-13

申请号：US10988692

申请日：2004-11-15

申请人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi

发明人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

公开(公告)号：US06540841B1

公开(公告)日：2003-04-01

申请号：US09607284

申请日：2000-06-30

申请人： Sudipto Ranendra Roy ,  Subhash Gupta ,  Simon Chooi ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho

发明人： Sudipto Ranendra Roy ,  Subhash Gupta ,  Simon Chooi ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho

IPC分类号： B08B700

CPC分类号： B08B1/04 ,  B08B3/04

摘要： A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface. After contaminants have been removed in this manner from the surface, the surface can be further cleaned by applying DI water.

摘要翻译： 提供了可用于清洁半导体衬底的外边缘的新方法和装置。 在本发明的第一实施例中，刷子安装在基板周围的基板的表面上，化学品通过其上安装有清洁刷的中空芯被供给到待清洁的表面。 待清洁的表面以相对高的速度旋转，从而使沉积在该表面（由刷子）上的化学物质残留在表面的边缘。 在本发明的第二实施例中，多孔辊安装在化学容器和待清洁的表面之间，待清洁的表面以相对较高的速度旋转。 因此，由界面多孔辊沉积在待清洗的表面上的化学物质保留在该表面的边缘，从而引起表面边缘的最佳清洁作用。 污染物以这种方式从表面除去后，可以通过加入去离子水进一步清洁表面。

公开(公告)号：US06365508B1

公开(公告)日：2002-04-02

申请号：US09618264

申请日：2000-07-18

申请人： Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi ,  Simon Chooi ,  Yakub Aliyu

发明人： Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi ,  Simon Chooi ,  Yakub Aliyu

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76826

摘要： A new method to avoid post-etch cleaning in a metallization process is described. An insulating layer is formed over a first metal line in a dielectric layer overlying a semiconductor substrate. A via opening is etched through the insulating layer to the first metal line whereby a polymer forms on sidewalls of the via opening. The polymer is treated with a fluorinating agent whereby the polymer is converted to an inert layer. Thereafter, a second metal line is formed within the via opening wherein the inert layer acts is as a barrier layer to complete the metallization process in the fabrication of an integrated circuit device.

摘要翻译： 描述了在金属化过程中避免蚀刻后清洁的新方法。 在覆盖半导体衬底的电介质层中的第一金属线上形成绝缘层。 通孔开口通过绝缘层蚀刻到第一金属线，由此在通孔开口的侧壁上形成聚合物。 用氟化剂处理聚合物，由此将聚合物转化为惰性层。 此后，在通孔开口内形成第二金属线，其中惰性层作为阻挡层，以在集成电路器件的制造中完成金属化工艺。

公开(公告)号：US06358821B1

公开(公告)日：2002-03-19

申请号：US09619376

申请日：2000-07-19

申请人： Subhash Gupta ,  Simon Chooi ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono

发明人： Subhash Gupta ,  Simon Chooi ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono

IPC分类号： H01L2122

CPC分类号： H01L21/3221 ,  C23C14/165 ,  H01L21/2885

摘要： A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.

摘要翻译： 一种防止半导体晶片上的铜传输的方法，包括以下步骤。 提供具有正面和背面的半导体晶片。 从包括铝，铝 - 铜，铝 - 硅和铝 - 铜 - 硅的组中选择的金属溅射在晶片的背面以形成一层金属。 背面溅射的铝层可以在低温下部分氧化，以进一步降低铜的渗透可能性，并且在随后的铜互连相关处理中也提供更大的灵活性。 一旦背面层就位，就可以照常处理晶片。 最后的背面研磨可以除去溅射的背面铝层。