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21 条记录 (耗时 0.019 秒)

    Method and device for gracious arbitration of access to a computer system resource
    1.
    发明授权
    Method and device for gracious arbitration of access to a computer system resource 失效
    用于访问计算机系统资源的亲和仲裁的方法和装置

    公开(公告)号：US5930486A

    公开(公告)日：1999-07-27

    申请号：US707884

    申请日：1996-09-09

    申请人： Lily Pao Looi ,  Nitin Borkar ,  Frank Verhoorn

    发明人： Lily Pao Looi ,  Nitin Borkar ,  Frank Verhoorn

    IPC分类号： G06F13/364 ,  G06F13/362

    CPC分类号： G06F13/364

    摘要： A computer system includes a priority arbitration scheme that prevents "hogging" of a bus by a priority agent. The computer system comprises at least one agent, at least one priority agent, a system resource, and a bus coupling the agent, priority agent, and system resource to one another. An arbiter is coupled to the bus, agent, and priority agent to receive request signals from the agent and the priority agent and to grant control of the bus to one of the agent and priority agent for access to the system resource. The priority agent is granted control of the bus whenever the priority agent asserts a request signal, as soon as the bus becomes next available. The priority agent relinquishes control of the bus to the agent, for a predetermined portion of the bus bandwidth, when a request signal is asserted by the agent.

    摘要翻译： 计算机系统包括优先权仲裁方案，其防止优先代理人对总线进行“占用”。 计算机系统包括至少一个代理，至少一个优先级代理，系统资源和将代理，优先级代理和系统资源彼此耦合的总线。 仲裁器耦合到总线，代理和优先级代理以从代理和优先级代理接收请求信号，并且将总线的控制权授予代理和优先级代理之一用于访问系统资源。 一旦总线变为下一个可用，优先权代理就会在优先权代理人断言一个请求信号时被控制总线。 当代理人断言请求信号时，优先权代理将总线的总线放弃到总线带宽的预定部分。

    Scalable distributed memory and I/O multiprocessor systems and associated methods
    5.
    发明申请
    Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
    可扩展分布式存储器和I / O多处理器系统及相关方法

    公开(公告)号：US20070106833A1

    公开(公告)日：2007-05-10

    申请号：US11422542

    申请日：2006-06-06

    申请人： Linda Rankin ,  Paul Pierce ,  Gregory Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard Hofsheier ,  Nitin Borkar

    发明人： Linda Rankin ,  Paul Pierce ,  Gregory Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard Hofsheier ,  Nitin Borkar

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4022 ,  G06F13/4027

    摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

    摘要翻译： 多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。 在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥接器。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。 使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。 此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。 处理器内存总线，时钟和复位逻辑都保持不变。

    Low jitter external clocking
    10.
    发明申请
    Low jitter external clocking 审中-公开
    低抖动外部时钟

    公开(公告)号：US20050007163A1

    公开(公告)日：2005-01-13

    申请号：US10912486

    申请日：2004-08-05

    申请人： Rajendran Nair ,  Gregory Dermer ,  Stephen Mooney ,  Nitin Borkar

    发明人： Rajendran Nair ,  Gregory Dermer ,  Stephen Mooney ,  Nitin Borkar

    IPC分类号： G06F1/10 ,  H03K5/24 ,  H03B1/00

    CPC分类号： G06F1/10 ,  H03K5/2481

    摘要： A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

    摘要翻译： 公开了一种低抖动外部时钟系统和方法。 根据本发明的一个实施例，在第一时钟信号线和第二时钟信号线上接收差分时钟信号。 耦合到第一时钟信号线和第二时钟信号线的差分放大器将差分时钟信号放大成单端输出时钟信号。