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10 条记录 (耗时 0.027 秒)

    Silicon recess improvement through improved post implant resist removal and cleans
    1.
    发明授权
    Silicon recess improvement through improved post implant resist removal and cleans 有权
    通过改进的后植入物抗蚀剂去除和清洁来改善硅凹槽

    公开(公告)号：US07371691B2

    公开(公告)日：2008-05-13

    申请号：US10901827

    申请日：2004-07-29

    申请人： Lindsey H. Hall ,  Trace Q. Hurd ,  Deborah J. Riley

    发明人： Lindsey H. Hall ,  Trace Q. Hurd ,  Deborah J. Riley

    IPC分类号： H01L21/3065

    CPC分类号： H01L21/31138 ,  G03F7/423 ,  G03F7/427 ,  H01L21/31133 ,  H01L21/8238 ,  H01L29/6659

    摘要： The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.

    摘要翻译： 本发明提供一种在减少硅损耗的同时制造半导体器件200的工艺。 在一个方面，该方法包括从邻近门240的半导体衬底235去除光致抗蚀剂层270并用湿清洁溶液清洁半导体衬底。 去除步骤包括使光致抗蚀剂层270经受等离子体灰分。 等离子体灰去除形成在光致抗蚀剂层270上的外壳275的至少一部分，但留下光致抗蚀剂层270的大部分。 光致抗蚀剂层270在等离子体灰之后进行湿法蚀刻，其除去光致抗蚀剂层270的主要部分。

    Versatile system for wafer edge remediation
    8.
    发明授权
    Versatile system for wafer edge remediation 有权
    晶圆边缘修复的多功能系统

    公开(公告)号：US07195679B2

    公开(公告)日：2007-03-27

    申请号：US10601016

    申请日：2003-06-21

    申请人： Changfeng Xia ,  Trace Q. Hurd

    发明人： Changfeng Xia ,  Trace Q. Hurd

    IPC分类号： B08B3/02

    CPC分类号： H01L21/67051 ,  B08B3/02 ,  B08B3/102 ,  B08B5/02 ,  Y10S134/902

    摘要： The present invention provides a system (200, 300) for remediating aberrations along the perimeter of a semiconductor wafer (202). The system includes a cleaning apparatus (204) within which the wafer is spun within a confined area. A chuck (208) defines the confined area, having a sidewall that extends above the upper surface (214) of the wafer and surrounds the perimeter of the wafer. The chuck also has a bottom wall, with an aperture formed therein, beneath the wafer. The system includes an isolation barrier (220), disposed atop the bottom wall of the chuck and around the aperture, in proximity to the lower surface so of the wafer. This forms a narrow gap (226) between the barrier and the wafer. A pressurized source forcefully directs a gas (218) at and along the lower surface of the wafer. The system also includes a remediation solution (228) that is applied to the upper surface of the wafer. The solution is forced into a well (230) formed between the chuck sidewall and the perimeter of the wafer, such that the solution bathes the perimeter of the wafer.

    摘要翻译： 本发明提供一种用于补救沿着半导体晶片（202）周边的像差的系统（200,300）。 该系统包括清洁设备（204），在该清洁设备内，晶片在限制区域内旋转。 卡盘（208）限定约束区域，其具有在晶片的上表面（214）上方延伸并且围绕晶片的周边的侧壁。 卡盘还具有底壁，其中形成有孔，在晶片下方。 该系统包括隔离屏障（220），该隔离屏障（220）设置在卡盘的底壁的上方并且围绕孔径，靠近晶片的下表面。 这在屏障和晶片之间形成窄的间隙（226）。 加压源强制地引导位于晶片下表面的气体（218）。 该系统还包括施加到晶片的上表面的补救解决方案（228）。 溶液被迫进入形成在卡盘侧壁和晶片的周边之间的孔（230）中，使得溶液洗涤晶片的周边。

    Surface treatment of copper to improve interconnect formation
    9.
    发明授权
    Surface treatment of copper to improve interconnect formation 有权
    铜的表面处理以改善互连形成

    公开(公告)号：US06995088B2

    公开(公告)日：2006-02-07

    申请号：US10848219

    申请日：2004-05-18

    申请人： Sanjeev Aggarwal ,  Lindsey Hall ,  Trace Q. Hurd

    发明人： Sanjeev Aggarwal ,  Lindsey Hall ,  Trace Q. Hurd

    IPC分类号： H01L21/44

    CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76873

    摘要： The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a copper seed layer (110) located over a semiconductor substrate with a protective agent (120) to form a protective layer (125). The method also includes placing the semiconductor substrate in an acid bath (145) to remove the protective layer. The method further includes electrochemically depositing a second copper layer (155) on the copper seed layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

    摘要翻译： 在一个实施例中，本发明提供了一种在半导体衬底（105）上形成铜层（100）的方法。 该方法包括用保护剂（120）涂覆位于半导体衬底上的铜籽晶层（110）以形成保护层（125）。 该方法还包括将半导体衬底放置在酸浴（145）中以去除保护层。 该方法还包括在铜籽晶层上电化学沉积第二铜层（155）。 这样的方法及其导电结构可有利地用于制造包括铜互连的集成电路的方法中。

    Contamination control for embedded ferroelectric device fabrication processes
    10.
    发明授权
    Contamination control for embedded ferroelectric device fabrication processes 失效
    嵌入式铁电元件制造工艺的污染控制

    公开(公告)号：US06709875B2

    公开(公告)日：2004-03-23

    申请号：US09925201

    申请日：2001-08-08

    申请人： Stephen R. Gilbert ,  Trace Q. Hurd ,  Laura W. Mirkarimi ,  Scott Summerfelt ,  Luigi Colombo

    发明人： Stephen R. Gilbert ,  Trace Q. Hurd ,  Laura W. Mirkarimi ,  Scott Summerfelt ,  Luigi Colombo

    IPC分类号： H01G706

    CPC分类号： H01L21/6708 ,  H01L21/31122 ,  H01L21/32136 ,  H01L27/0805 ,  H01L27/11502 ,  H01L28/55

    摘要： A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

    摘要翻译： 描述了与标准CMOS制造工艺不兼容的铁电体器件污染物质（例如，Pb，Zr，Ti和Ir）被严格控制的铁电器件制造工艺。 特别地，已经开发了特定的蚀刻化学物质，以在形成铁电体器件之后从衬底的背面和边缘表面去除不相容的物质。 此外，牺牲层可以设置在衬底的底部和边缘表面（以及在一些实施例中，前侧边缘排除区域表面）之上，以帮助去除难以蚀刻的污染物（例如Ir）。 以这种方式，铁电体器件的制造工艺可以与标准的半导体制造工艺集成在一起，由此铁电器件可以与半导体集成电路一起形成，而没有通过共享设备（例如，步进器，计量工具和 喜欢）。