利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

179 条记录 (耗时 0.023 秒)

    Memory cell configuration and method for its production
    1.
    发明授权
    Memory cell configuration and method for its production 失效
    存储单元配置及其生产方法

    公开(公告)号：US06300652B1

    公开(公告)日：2001-10-09

    申请号：US08755456

    申请日：1996-11-22

    申请人： Lothar Risch ,  Franz Hofmann ,  Rainer Bruchhaus ,  Wolfram Wersing

    发明人： Lothar Risch ,  Franz Hofmann ,  Rainer Bruchhaus ,  Wolfram Wersing

    IPC分类号： H01L27108

    CPC分类号： H01L27/11502 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

    摘要： A memory cell configuration and a method for its production include stacked capacitors and use a vertical storage capacitor having a ferroelectric or paraelectric storage dielectric. In order to produce the storage capacitor, a dielectric layer for the storage dielectric is produced over the whole area. The dielectric layer is subsequently structured and first electrodes and second electrodes for the storage capacitors are formed. The invention is suitable for Gbit DRAMs and for nonvolatile memories.

    摘要翻译： 存储单元配置及其制造方法包括堆叠电容器，并且使用具有铁电或顺电存储电介质的垂直存储电容器。 为了制造存储电容器，在整个区域上产生用于存储电介质的电介质层。 随后构造电介质层，形成用于存储电容器的第一电极和第二电极。 本发明适用于Gbit DRAM和非易失性存储器。

    DRAM cell circuit
    3.
    发明授权
    DRAM cell circuit 有权
    DRAM单元电路

    公开(公告)号：US06362502B1

    公开(公告)日：2002-03-26

    申请号：US09692118

    申请日：2000-10-19

    申请人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Franz Hofmann

    发明人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Franz Hofmann

    IPC分类号： H01L27108

    CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10876

    摘要： A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.

    摘要翻译： 存储单元包含存储晶体管和转移晶体管。 转移晶体管的栅电极和存储晶体管的控制栅电极连接到字线。 存储晶体管具有通过第一介电层与存储晶体管的沟道区隔离并与转移晶体管的第一源极/漏极区连接的浮栅电极。 控制栅电极通过第二电介质层与浮置栅电极隔离。 存储晶体管的第一源/漏区连接到位线。 存储器和转移晶体管优选地具有不同的导电类型。 在写入信息期间，传输晶体管处于导通状态，并且存储晶体管处于截止状态。 在读出信息期间，传输晶体管处于截止状态，并且存储晶体管处于导通状态。

    Method of producing a read-only storage cell arrangement
    4.
    发明授权
    Method of producing a read-only storage cell arrangement 失效
    制造只读存储单元布置的方法

    公开(公告)号：US5998261A

    公开(公告)日：1999-12-07

    申请号：US973701

    申请日：1997-12-08

    申请人： Franz Hofmann ,  Wolfgang Rosner ,  Wolfgang Krautschneider ,  Lothar Risch

    发明人： Franz Hofmann ,  Wolfgang Rosner ,  Wolfgang Krautschneider ,  Lothar Risch

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/11517 ,  H01L27/115

    摘要： An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.

    摘要翻译： PCT No.PCT / DE96 / 01117 Sec。 371 1997年12月8日第 102（e）日期1997年12月8日PCT提交1996年6月25日PCT公布。 第WO97 / 02599号公报 日期1997年1月23日在半导体衬底（优选单晶硅）或SOI衬底的硅层中制造的电可写和可擦除的只读存储单元布置。 具有存储单元的单元阵列设置在半导体基板的主表面上。 每个存储单元包括垂直于主表面的MOS晶体管，并且除了源极/漏极区域和布置在其之间的沟道区域之外还包括第一电介质，浮动栅极，第二电介质和控制栅极。 多个基本上平行的带状沟槽设置在单元阵列中。 垂直MOS晶体管布置在沟槽的侧面。 存储单元在每种情况下都布置在沟槽的相对侧面上。

    Read-only memory cell array and process for manufacturing it
    5.
    发明授权
    Read-only memory cell array and process for manufacturing it 失效
    只读存储单元阵列及其制造过程

    公开(公告)号：US5920099A

    公开(公告)日：1999-07-06

    申请号：US913332

    申请日：1997-09-11

    申请人： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann

    发明人： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann

    IPC分类号： H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/1126 ,  H01L27/112

    摘要： A read-only memory cell array has a plurality of individual memory cells which each have a MOS transistor and which are arranged in rows running in parallel. In this context, adjacent rows run alternately at the bottom of the longitudinal trenches (6) and between adjacent longitudinal trenches (6) respectively and are insulated with respect to one another. The read-only memory cell array can be manufactured by self-aligning process steps with an area of 2 F.sup.2 (F: minimum structure size) being required per memory cell.

    摘要翻译： PCT No.PCT / DE96 / 00380 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT PCT 1996年3月4日PCT公布。 公开号WO96 / 29739 日期1996年9月26日只读存储单元阵列具有多个单独的存储单元，每个单独存储单元具有MOS晶体管并且并行排列。 在这种情况下，相邻的行分别在纵向沟槽（6）的底部和相邻的纵向沟槽（6）之间交替地延伸并相对于彼此绝缘。 只读存储单元阵列可以通过每个存储单元需要2 F2（F：最小结构尺寸）面积的自对准工艺步骤来制造。

    Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
    6.
    发明授权
    Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells 失效
    包含自放大动态MOS晶体管存储单元的制造和布置方法

    公开(公告)号：US5710072A

    公开(公告)日：1998-01-20

    申请号：US737236

    申请日：1996-11-18

    申请人： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann

    发明人： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann

    IPC分类号： H01L27/08 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L21/336

    CPC分类号： H01L27/10844 ,  H01L27/0629 ,  H01L27/108

    摘要： To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.

    摘要翻译： PCT No.PCT / EP95 / 01656 Sec。 371日期：1996年11月18日 102（e）1996年11月18日PCT PCT 1995年5月2日PCT公布。 公开号WO95 / 31828 日期：1995年11月23日为了制造包含自放大动态MOS晶体管存储单元的布置，每个包括选择晶体管，存储晶体管和二极管结构，选择晶体管和存储晶体管通过公共节点串联连接， 二极管结构连接在存储晶体管的公共节点和栅电极（10）之间，选择晶体管和存储晶体管形成为垂直MOS晶体管。 为此，产生其中产生沟槽（5,6）并且设置有栅极电介质（7,8）和栅电极（9,10））的适当掺杂区（2,3,4）的垂直序列， 特别是通过LPCVD外延或通过分子束外延。

    Read-only memory cell arrangement and method for its production
    8.
    发明授权
    Read-only memory cell arrangement and method for its production 失效
    只读存储单元布置及其生产方法

    公开(公告)号：US5920778A

    公开(公告)日：1999-07-06

    申请号：US913740

    申请日：1997-09-23

    申请人： Wolfgang Rosner ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Lothar Risch

    发明人： Wolfgang Rosner ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Lothar Risch

    IPC分类号： H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/11273 ,  H01L27/112

    摘要： In a read-only memory cell arrangement having first memory cells which contain a vertical MOS transistor, and having second memory cells which do not contain vertical MOS transistors, the memory cells are arranged along opposite flanks of strip-shaped parallel insulation trenches (16). The width of the insulation trenches (16) is preferably equal to their separation, so that the memory cell arrangement can be produced with a space requirement of 2F.sup.2 per memory cell, F being the minimum structure size in the respective technology.

    摘要翻译： PCT No.PCT / DE96 / 00614 Sec。 371日期1997年9月23日 102（e）1997年9月23日PCT PCT 1996年4月9日PCT公布。 公开号WO96 / 3351300 日期1996年10月24日在具有包含垂直MOS晶体管的第一存储单元且具有不包含垂直MOS晶体管的第二存储单元的只读存储单元布置中，存储单元沿着带状平行的相对侧布置 绝缘沟槽（16）。 绝缘沟槽（16）的宽度优选等于它们的间隔，使得可以以每个存储单元的空间要求为2F2来生产存储单元布置，F是相应技术中的最小结构尺寸。

    Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof
    9.
    发明授权
    Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof 失效
    具有至少一个CMOS-NAND门的集成电路结构及其制造方法

    公开(公告)号：US5559353A

    公开(公告)日：1996-09-24

    申请号：US332737

    申请日：1994-11-01

    申请人： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

    发明人： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

    IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L27/092 ,  H03K19/0948 ,  H01L29/78

    CPC分类号： H03K19/0948 ,  H01L21/76294 ,  H01L27/0922

    摘要： A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the source, channel and drain and that which has a sidewall at which a gate dielectric and a gate electrode are arranged. The complementary MOS transistors connected in parallel with one another are realized in a common layer sequence of the source, channel and drain. The layer sequences that form the series-connected transistors are arranged above one another. The circuit structure is manufactured by epitaxal definition of the layer sequences, such as by molecular beam epitaxy.

    摘要翻译： 第一MOS晶体管和第二MOS晶体管与彼此并联连接的第一互补MOS晶体管和第二互补MOS晶体管串联连接。 晶体管各自被实现为形成源极，沟道和漏极的垂直层序列，并且其具有设置栅极电介质和栅电极的侧壁。 在源极，沟道和漏极的公共层序列中实现彼此并联连接的互补MOS晶体管。 形成串联晶体管的层序列彼此重叠。 电路结构通过层序列的上层定义（例如通过分子束外延）来制造。

    DRAM memory cell
    10.
    发明授权
    DRAM memory cell 失效
    DRAM存储单元

    公开(公告)号：US07368752B2

    公开(公告)日：2008-05-06

    申请号：US10839800

    申请日：2004-05-06

    申请人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    发明人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    IPC分类号： H01L27/108 ,  H01L29/12 ,  H01L31/112

    CPC分类号： H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

    摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

    摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。