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    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    4.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US07226824B2

    公开(公告)日：2007-06-05

    申请号：US10918818

    申请日：2004-08-13

    申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    CARBON CONTROLLED FIXED CHARGE PROCESS
    6.
    发明申请
    CARBON CONTROLLED FIXED CHARGE PROCESS 审中-公开
    碳控制固定充电过程

    公开(公告)号：US20090011581A1

    公开(公告)日：2009-01-08

    申请号：US12212502

    申请日：2008-09-17

    申请人： Cory E. Weber ,  Keith E. Zawadzki

    发明人： Cory E. Weber ,  Keith E. Zawadzki

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26506 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/823807

    摘要： Carbon may be implanted into a p-type silicon channel to form a carbon region in an n-type metal oxide semiconductor (NMOS) transistor. After an annealing process, the implanted carbon may diffuse from the channel into an interface of a gate dielectric layer and the channel. The diffusion may cause an increase in fixed charge at the silicon surface. Thus, the threshold voltage of the NMOS transistor may be reduced.

    摘要翻译： 可以将碳注入到p型硅通道中以在n型金属氧化物半导体（NMOS）晶体管中形成碳区。 在退火处理之后，注入的碳可以从沟道扩散到栅极介电层和沟道的界面。 扩散可能导致硅表面固定电荷的增加。 因此，可以减小NMOS晶体管的阈值电压。

    Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantation
    9.
    发明申请
    Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantation 审中-公开
    通过使用离子注入引入压缩金属栅极应力来驱动三栅极MOSFET的电流增强

    公开(公告)号：US20110147804A1

    公开(公告)日：2011-06-23

    申请号：US12646673

    申请日：2009-12-23

    申请人： Rishabh Mehandru ,  Cory E. Weber ,  Ashutosh Ashutosh ,  Jack Hwang

    发明人： Rishabh Mehandru ,  Cory E. Weber ,  Ashutosh Ashutosh ,  Jack Hwang

    IPC分类号： H01L29/78 ,  H01L21/20

    CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L29/66795 ,  H01L29/785

    摘要： A semiconductor device comprises a fin and a metal gate film. The fin is formed on a surface of a semiconductor material. The metal gate film formed on the fin and comprises ions implanted in the metal gate film to form a compressive stress within the metal gate. In one exemplary embodiment, the surface of the semiconductor material comprises a (100) crystalline lattice orientation, and an orientation of the fin is along a direction with respect to the crystalline lattice of the semiconductor. In another exemplary embodiment, the surface of the semiconductor material comprises a (100) crystalline lattice orientation, and the orientation of the fin is along a direction with respect to the crystalline lattice of the semiconductor. The fin comprises an out-of-plane compression that is generated by the compressive stress within the metal gate film.

    摘要翻译： 半导体器件包括翅片和金属栅极膜。 翅片形成在半导体材料的表面上。 金属栅极膜形成在翅片上并且包括注入金属栅极膜中的离子，以在金属栅极内形成压应力。 在一个示例性实施例中，半导体材料的表面包括（100）晶格取向，并且鳍的取向相对于半导体的晶格沿着<100>方向。 在另一个示例性实施例中，半导体材料的表面包括（100）晶格取向，鳍的取向相对于半导体的晶格沿着<110>方向。 翅片包括由金属栅膜内的压应力产生的平面外压缩。

    NANOWIRE STRUCTURES HAVING WRAP-AROUND CONTACTS
    10.
    发明申请
    NANOWIRE STRUCTURES HAVING WRAP-AROUND CONTACTS 审中-公开
    具有缠绕接头的纳米结构

    公开(公告)号：US20140209855A1

    公开(公告)日：2014-07-31

    申请号：US13995914

    申请日：2011-12-23

    申请人： Stephen M. Cea ,  Cory E. Weber ,  Patrick H. Keys ,  Seiyon Kim ,  Michael G. Haverty ,  Sadasivan Shankar

    发明人： Stephen M. Cea ,  Cory E. Weber ,  Patrick H. Keys ,  Seiyon Kim ,  Michael G. Haverty ,  Sadasivan Shankar

    IPC分类号： H01L29/775 ,  H01L29/66

    摘要： Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

    摘要翻译： 描述具有环绕触点的纳米线结构。 例如，纳米线半导体器件包括设置在衬底之上的纳米线。 沟道区域设置在纳米线中。 通道区域具有与长度正交的长度和周长。 栅电极堆叠围绕通道区域的整个周边。 一对源极和漏极区域设置在沟道区域的任一侧上的纳米线中。 源极和漏极区域中的每一个具有与沟道区域的长度正交的周长。 第一接触件完全围绕源区域的周边。 第二触点完全围绕漏区的周边。