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公开(公告)号：US07566605B2
公开(公告)日：2009-07-28
申请号：US11395939
申请日：2006-03-31
IPC分类号： H01L21/8238 , H01L21/425
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7846 , H01L29/7848
摘要： A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.
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2.发明授权Epitaxial silicon germanium for reduced contact resistance in field-effect transistors 有权外延硅锗，用于降低场效应晶体管的接触电阻公开(公告)号：US07851291B2
公开(公告)日：2010-12-14
申请号：US12454975
申请日：2009-05-26
IPC分类号： H01L21/8238 , H01L21/425
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7846 , H01L29/7848
摘要： A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.
摘要翻译： 描述了一种用于选择性地消除具有凹陷的外延SiGe源极和漏极区域的n沟道晶体管的沟道应力的方法。 这增加了n沟道晶体管的电子迁移率，而不影响p沟道晶体管的应变。 当形成硅化物时，SiGe提供较低的电阻。
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3.发明申请Epitaxial silicon germanium for reduced contact resistance in field-effect transistors 有权外延硅锗，用于降低场效应晶体管的接触电阻公开(公告)号：US20090230480A1
公开(公告)日：2009-09-17
申请号：US12454975
申请日：2009-05-26
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7846 , H01L29/7848
摘要： A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.
摘要翻译： 描述了一种用于选择性地消除具有凹陷的外延SiGe源极和漏极区域的n沟道晶体管的沟道应力的方法。 这增加了n沟道晶体管的电子迁移率，而不影响p沟道晶体管的应变。 当形成硅化物时，SiGe提供较低的电阻。
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公开(公告)号：US20140291615A1
公开(公告)日：2014-10-02
申请号：US14302371
申请日：2014-06-11
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L29/15
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号：US20120199813A1
公开(公告)日：2012-08-09
申请号：US13450359
申请日：2012-04-18
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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6.发明授权Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域公开(公告)号：US07888221B2
公开(公告)日：2011-02-15
申请号：US12229459
申请日：2008-08-22
申请人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
发明人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/7391
摘要： The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
摘要翻译： 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区。
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公开(公告)号：US07316949B2
公开(公告)日：2008-01-08
申请号：US11248737
申请日：2005-10-11
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译： 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。
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8.发明授权CMOS devices with a single work function gate electrode and method of fabrication 有权CMOS器件具有单功能功能的栅电极和制造方法公开(公告)号：US08294180B2
公开(公告)日：2012-10-23
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。
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公开(公告)号：US08183556B2
公开(公告)日：2012-05-22
申请号：US11305452
申请日：2005-12-15
申请人： Suman Datt{dot over (a)} , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amlan , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datt{dot over (a)} , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amlan , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L21/84
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号：US07989280B2
公开(公告)日：2011-08-02
申请号：US12338839
申请日：2008-12-18
申请人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
发明人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译： 描述了III-V族半导体器件及其制造方法。 高k电介质通过硫族化物区域连接到约束区域。
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