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公开(公告)号：US20250087600A1
公开(公告)日：2025-03-13
申请号：US18808098
申请日：2024-08-19
Applicant: MACRONIX International Co., Ltd.
Inventor： Cheng-Hsien Lu , Ming-Hsiu Lee , Dai-Ying Lee
IPC: H01L23/00 , H01L21/3205 , H01L21/78 , H01L25/18 , H10B80/00
Abstract: A semiconductor bonded structure including a first semiconductor chip, at least one second semiconductor chip, a stress adjusting structure, and a circuit layer is provided. The at least one second semiconductor chip is disposed on the first semiconductor chip and electrically connected to the first semiconductor chip. The stress adjusting structure is disposed in at least one of the first semiconductor chip and the at least one second semiconductor chip. The circuit layer is disposed on the at least one second semiconductor chip and the circuit layer is electrically connected to the at least one second semiconductor chip. A fabricating method of the semiconductor bonded structure is also provided. The semiconductor bonded structure may be applied to the fabrication of 3D NAND flash memory with high performance and high capacity.
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公开(公告)号：US12046286B1
公开(公告)日：2024-07-23
申请号：US17847810
申请日：2022-06-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yun-Yuan Wang , Wei-Chen Chen , Dai-Ying Lee , Ming-Hsiu Lee
CPC classification number: G11C16/0483 , G11C16/102 , G11C16/24 , G11C16/26 , G11C16/3404
Abstract: A semiconductor circuit and an operating method for the same are provided. The semiconductor circuit includes strings. The strings include a first string and a second string. The first string includes a first device unit and a second device unit in series. The first string has a weight signal W1. The first device unit has an input signal A. The second device unit has an input signal B. The second string includes a third device unit and a fourth device unit in series. The second string has a weight signal W2. The third device unit has an input signal Ā. The fourth device unit has an input signal B. An output signal of the semiconductor circuit is a sum of output string signals of the strings.
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公开(公告)号：US20170206960A1
公开(公告)日：2017-07-20
申请号：US15134438
申请日：2016-04-21
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chao-I Wu , Dai-Ying Lee , Ming-Hsiu Lee , Tien-Yen Wang
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C2013/0066 , G11C2213/52 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1633
Abstract: A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a sidewall electrode portion extending upwardly from the bottom electrode portion and between the memory film and the bottom electrode portion. A width of the sidewall electrode portion and a width of the memory film are smaller than a width of the bottom electrode portion.
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公开(公告)号：US09711217B1
公开(公告)日：2017-07-18
申请号：US15134438
申请日：2016-04-21
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chao-I Wu , Dai-Ying Lee , Ming-Hsiu Lee , Tien-Yen Wang
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C2013/0066 , G11C2213/52 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1633
Abstract: A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a sidewall electrode portion extending upwardly from the bottom electrode portion and between the memory film and the bottom electrode portion. A width of the sidewall electrode portion and a width of the memory film are smaller than a width of the bottom electrode portion.
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公开(公告)号：US09583536B2
公开(公告)日：2017-02-28
申请号：US14806832
申请日：2015-07-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Erh-Kun Lai , Chao-I Wu , Yu-Hsuan Lin , Dai-Ying Lee
CPC classification number: H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1641 , H01L45/1691
Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.
Abstract translation: 提供具有阵列区域和周边区域的存储器件。 存储器件包括衬底，形成在衬底中的隔离层，形成在阵列区域中的隔离层上的第一掺杂区域，形成在第一掺杂区域上的第二掺杂区域，形成在第二掺杂区域上的金属硅化物层 以及形成在金属硅化物层上的金属硅化物层。
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Patent Agency Ranking
公开(公告)号：US20170025473A1
公开(公告)日：2017-01-26
申请号：US14806832
申请日：2015-07-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Erh-Kun Lai , Chao-I Wu , Yu-Hsuan Lin , Dai-Ying Lee
CPC classification number: H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1641 , H01L45/1691
Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.
Abstract translation: 提供具有阵列区域和周边区域的存储器件。 存储器件包括衬底，形成在衬底中的隔离层，形成在阵列区域中的隔离层上的第一掺杂区域，形成在第一掺杂区域上的第二掺杂区域，形成在第二掺杂区域上的金属硅化物层 以及形成在金属硅化物层上的金属硅化物层。
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公开(公告)号：US12255136B2
公开(公告)日：2025-03-18
申请号：US17748111
申请日：2022-05-19
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Cheng-Hsien Lu , Yun-Yuan Wang , Ming-Hsiu Lee , Dai-Ying Lee
IPC: H01L23/522 , H01L23/532
Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.
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公开(公告)号：US12254915B1
公开(公告)日：2025-03-18
申请号：US18240852
申请日：2023-08-31
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Dai-Ying Lee , Teng-Hao Yeh , Wei-Chen Chen , Rachit Dobhal , Zefu Zhao , Chee-Wee Liu
Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.
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公开(公告)号：US12114514B2
公开(公告)日：2024-10-08
申请号：US18519230
申请日：2023-11-27
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min Lee , Erh-Kun Lai , Dai-Ying Lee , Yu-Hsuan Lin , Po-Hao Tseng , Ming-Hsiu Lee
CPC classification number: H10B63/845 , H10B61/22 , H10B63/34 , H10N50/01 , H10N70/066
Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.
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公开(公告)号：US11482282B2
公开(公告)日：2022-10-25
申请号：US17191944
申请日：2021-03-04
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yun-Yuan Wang , Dai-Ying Lee
Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array including a plurality of memory cells; a plurality of bit lines coupled to the memory array; a plurality of word lines coupled to the memory array; and a plurality of conductance controllable units coupled to the memory array; wherein a memory cell group and at least one conductance controllable unit among the conductance controllable units form a logic operation unit, and a logic operation function of the logic operation unit is determined by an equivalent conductance of the at least one conductance controllable unit.
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