公开(公告)号：US09257154B2

公开(公告)日：2016-02-09

申请号：US13689386

申请日：2012-11-29

Applicant: Micron Technology, Inc.

Inventor： Jaekwan Park

IPC: G11C5/14 ,  G11C7/08 ,  G11C7/12 ,  G11C16/24 ,  G11C16/26 ,  G11C7/14 ,  G11C7/06

CPC classification number: G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063

Abstract: Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Abstract translation: 描述用于补偿源电压的装置和方法。 示例性设备包括耦合到存储器单元的源和耦合到存储单元的读写电路。 该装置还包括耦合到源的节点和读写电路的感测电流发生器，该感测电流发生器被配置为响应于该读写电路的节点的电压来控制读写电路的提供感测电流 资源。

公开(公告)号：US20190172506A1

公开(公告)日：2019-06-06

申请号：US16270495

申请日：2019-02-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaekwan Park

IPC: G11C5/14 ,  G11C7/22 ,  G11C7/06 ,  G11C7/14 ,  G11C16/26 ,  G11C16/24 ,  G11C7/12 ,  G11C7/08

CPC classification number: G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063

Abstract: Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

公开(公告)号：US20160155481A1

公开(公告)日：2016-06-02

申请号：US15019687

申请日：2016-02-09

Applicant: Micron Technology, Inc.

Inventor： Jaekwan Park

IPC: G11C5/14 ,  G11C7/06

CPC classification number: G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063

Abstract: Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Abstract translation: 描述用于补偿源电压的装置和方法。 示例性设备包括耦合到存储器单元的源和耦合到存储单元的读写电路。 该装置还包括耦合到源的节点和读写电路的感测电流发生器，该感测电流发生器被配置为响应于该读写电路的节点的电压来控制读写电路的提供感测电流 资源。

公开(公告)号：US10381080B2

公开(公告)日：2019-08-13

申请号：US15280301

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Feng Pan ,  Jaekwan Park ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/26 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

公开(公告)号：US10204663B2

公开(公告)日：2019-02-12

申请号：US15454975

申请日：2017-03-09

Applicant: Micron Technology, Inc.

Inventor： Jaekwan Park

IPC: G11C5/14 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C16/24 ,  G11C16/26 ,  G11C7/14 ,  G11C7/22

Abstract: Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source cooled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node or the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

公开(公告)号：US09595303B2

公开(公告)日：2017-03-14

申请号：US15019687

申请日：2016-02-09

Applicant: Micron Technology, Inc.

Inventor： Jaekwan Park

IPC: G11C7/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C16/24 ,  G11C16/26 ,  G11C7/14

CPC classification number: G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063

Abstract: Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Abstract translation: 描述用于补偿源电压的装置和方法。 示例性设备包括耦合到存储器单元的源和耦合到存储单元的读写电路。 该装置还包括耦合到源的节点和读写电路的感测电流发生器，该感测电流发生器被配置为响应于该读写电路的节点的电压来控制读写电路的提供感测电流 资源。

公开(公告)号：US09460792B2

公开(公告)日：2016-10-04

申请号：US14518807

申请日：2014-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Jaekwan Park ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/0483 ,  G11C8/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.

Abstract translation: 描述了分段SGS线的装置和方法。 示例性装置可以包括存储器块的第一和第二多个存储器子块。 该装置可以包括与第一多个存储器子块相关联的第一选择栅极控制线和与第二多个存储器子块相关联的第二选择栅极控制线。 第一选择栅极控制线可以耦合到第一多个存储器子块的第一多个选择栅极开关。 第二选择栅极控制线可以耦合到第二多个存储器子块的第二多个选择栅极开关。 第一和第二多个选择栅极开关可以耦合到源极。 该装置可以包括与每个第一和第二多个存储器子块相关联的多个存储器访问线。

公开(公告)号：US20140146620A1

公开(公告)日：2014-05-29

申请号：US13689386

申请日：2012-11-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaekwan Park

IPC: G11C5/14 ,  G11C7/06

CPC classification number: G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063

Abstract: Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Abstract translation: 描述用于补偿源电压的装置和方法。 示例性设备包括耦合到存储器单元的源和耦合到存储单元的读写电路。 该装置还包括耦合到源的节点和读写电路的感测电流发生器，该感测电流发生器被配置为响应于该读写电路的节点的电压来控制读写电路的提供感测电流 资源。

公开(公告)号：US11145370B2

公开(公告)日：2021-10-12

申请号：US17065655

申请日：2020-10-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Jaekwan Park ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/26 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

公开(公告)号：US10803945B2

公开(公告)日：2020-10-13

申请号：US16457611

申请日：2019-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Jaekwan Park ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/26 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.