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公开(公告)号：US06528405B1
公开(公告)日：2003-03-04
申请号：US09506844
申请日：2000-02-18
IPC分类号： H01L2128
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/7784
摘要： An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant areas, extending at least into the buffer, are formed to define an implant free area in the device channel between the source and drain. Source and drain metal contacts are positioned on an upper surface of the central layer. Several layers of insulation and dielectric are positioned over the device and a gate opening is formed and filled with gate metal. During epitaxial growth, the doped cap layer is tailored with a thickness and a doping to optimize channel performance including gate-drain breakdown voltage and channel resistance.
摘要翻译： 增强型RF器件和制造方法包括：化合物半导体层的堆叠，包括限定器件沟道的中心层，掺杂的覆盖层和在衬底上外延生长的缓冲层。 形成至少延伸到缓冲器中的源极和漏极注入区域，以在源极和漏极之间的器件沟道中限定无植入区域。 源极和漏极金属触点位于中心层的上表面上。 绝缘和电介质的几层位于器件上方，并形成栅极开口并填充栅极金属。 在外延生长期间，掺杂的覆盖层是通过厚度和掺杂来调整的，以优化沟道性能，包括栅 - 漏击穿电压和沟道电阻。
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公开(公告)号：US06893947B2
公开(公告)日：2005-05-17
申请号：US10179769
申请日：2002-06-25
申请人： Marino J. Martinez , Ernest Schirmann , Olin L. Hartin , Colby G. Rampley , Mariam G. Sadaka , Charles E. Weitzel , Julio Costa
发明人： Marino J. Martinez , Ernest Schirmann , Olin L. Hartin , Colby G. Rampley , Mariam G. Sadaka , Charles E. Weitzel , Julio Costa
IPC分类号： H01L21/285 , H01L21/337 , H01L29/80 , H01L21/22
CPC分类号： H01L29/66924 , H01L21/28587 , H01L29/802
摘要： A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.
摘要翻译： 提供了一种制造具有改进的栅极特性的RF增强型FET（30）的方法。 该方法包括以下步骤：提供（131）具有形成在其上的半导体层（32-35）的堆叠的衬底（31），所述堆叠包括限定器件沟道的覆盖层（35）和中心层（33） 在所述盖层上形成（103）光致抗蚀剂图案（58），由此限定掩蔽区域和未掩蔽区域，并且以任何顺序，（a）在所述未掩蔽区域中产生（105）植入区域（36,37） ，和（b）从未掩蔽区域移除（107）盖层。 通过不重叠地形成注入区域和盖子区域，可以实现具有低电流泄漏的装置。
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公开(公告)号：US07504677B2
公开(公告)日：2009-03-17
申请号：US11092264
申请日：2005-03-28
IPC分类号： H01L29/80 , H01L21/337
CPC分类号： H01L27/0605 , H01L23/4824 , H01L29/42316 , H01L29/7786 , H01L2924/0002 , H01L2924/3011 , H04B1/48 , H01L2924/00
摘要： Methods and apparatus are provided for RF switches (100, 200). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors (50, 112, 114). When used in pairs (112, 114) each has its source (74, 133) coupled to a first common RF I/O port (116) and drains coupled respectively to second and third RF I/O ports (118, 120), and gates (136, 138), coupled respectively to first and second control terminals (122, 124). The multi-gate regions (66, 68) of the FETs (50) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). Lightly doped n-regions (Ldd, Lds) are provided serially arranged between the spaced-apart multi-gate regions (66, 68), the lightly doped n-regions (Ldd, Lds) being separated by more heavily doped n-regions (84). Bias resistances (132, 134) are provided between the sources (72, 133) and control terminals (122, 124) so as to provide a DC path between the control terminals (122, 124) that maintains the source (72, 133) voltage at the proper bias potential for enhancement mode operation.
摘要翻译： 提供了用于RF开关（100,200）的方法和装置。 在优选实施例中，该装置包括一个或多个多栅极n沟道增强型FET晶体管（50,112,114）。 当成对使用时，每个都具有耦合到第一公共RF I / O端口（116）的源极（74,133）和分别耦合到第二和第三RF I / O端口（118,120）的漏极， 和分别耦合到第一和第二控制端（122,124）的门（136,138）。 FET（50）的多栅极区域（66,68）平行耦合，间隔开并且串联地布置在源极（72）和漏极（76）之间。 轻度掺杂的n区（Ldd，Lds）被串行地布置在间隔开的多栅极区（66,68）之间，轻掺杂的n-区（Ldd，Lds）被更重掺杂的n区分离（ 84）。 偏置电阻（132,134）设置在源极（72,133）和控制端子（122,124）之间，以便在维持源极（72,133）和控制端子（122,124）之间提供DC路径， 电压处于适当的偏置电位，用于增强模式操作。
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4.发明授权公开(公告)号：US07345545B2
公开(公告)日：2008-03-18
申请号：US11092070
申请日：2005-03-28
IPC分类号： H03F3/16
CPC分类号： H03G1/0088
摘要： Methods and apparatus are provided for RF switches (504, 612) integrated in a monolithic RF transceiver IC (500) and switched gain amplifier (600). Multi-gate n-channel enhancement mode FETs (50, 112, 114, Q1-3, Q4-6) are used with single gate FETs (150), resistors (Rb, Rg, Re, R1-R17) and capacitors (C1-C3) formed by the same manufacturing process. The multiple gates (68) of the FETs (50, 112, 114, Q1-3, Q4-6) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). When used in pairs (112, 114) to form a switch (504) for a transceiver (500) each FET has its source (74) coupled to an antenna RF I/O port (116, 501) and drains coupled respectively to second and third RF I/O ports (118, 120; 507, 521) leading to the receiver side (530) or transmitter side (532) of the transceiver (500). The gates (136, 138) are coupled to control ports (122, 124; 503, 505; 606, 608). When used in pairs (Q1-3, Q4-6) to form a variable switched attenuator, the first FET (Q1-3) is a pass device and the second FET (Q4-6) is a shunt device that respectively bridge two series resistors (R1, R2) and block a shunt resistor (R3) of a T-type attenuator.
摘要翻译： 为集成在单片RF收发器IC（500）和开关增益放大器（600）中的RF开关（504,612）提供了方法和装置。 多栅极n沟道增强型FET（50,112,114，Q 1-3，Q 4-6）与单栅极FET（150），电阻器（Rb，Rg，Re，R 1 -R 17） 和通过相同制造工艺形成的电容器（C 1 -C 3）。 FET（50,112,114，Q1-3，Q4-6）的多个栅极（68）被平行耦合，间隔开并且串联地布置在源极（72）和漏极（76）之间。 当成对使用（112,114）形成用于收发器（500）的开关（504）时，每个FET的源极（74）耦合到天线RF I / O端口（116,501），并且分别耦合到第二 以及通向收发器（500）的接收机侧（530）或发射机侧（532）的第三RF I / O端口（118,120; 507,521）。 门（136,138）被耦合到控制端口（122,124; 503,505; 606,608）。 当成对使用（Q 1 - 3，Q 4 - 6）以形成可变开关衰减器时，第一FET（Q1-3）是通过器件，第二FET（Q 4 - 6）是分流器件， 分别桥接两个串联电阻（R 1，R 2）并阻塞T型衰减器的分流电阻（R 3）。
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公开(公告)号：US08957496B2
公开(公告)日：2015-02-17
申请号：US13864729
申请日：2013-04-17
CPC分类号： H01L27/0203 , H01L21/76 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L23/585 , H01L23/645 , H01L27/08 , H01L28/10 , H01L29/402 , H01L29/404 , H01L2924/0002 , H01L2924/00
摘要： An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.
摘要翻译： 电子设备包括半导体衬底，设置在半导体衬底中并由半导体衬底支撑并包括电感器的电路块以及围绕电路块的不连续噪声隔离保护环。 不连续的噪声隔离保护环包括由半导体衬底支撑的金属环和设置在半导体衬底中的环形区域，具有掺杂剂浓度水平并且电耦合到金属环，以抑制半导体衬底中的噪声达到 电路。 金属环具有第一间隙，并且环形区域具有第二间隙。
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公开(公告)号：US07683733B2
公开(公告)日：2010-03-23
申请号：US12025315
申请日：2008-02-04
申请人： Qiang Li , Jonathan K. Abrokwah , Olin L. Hartin , Lianjun Liu
发明人： Qiang Li , Jonathan K. Abrokwah , Olin L. Hartin , Lianjun Liu
CPC分类号： H01F19/04 , H03H7/1775 , H03H7/42 , H03H2001/0064 , Y10T29/4902
摘要： An electronic assembly includes a substrate (66), a balun transformer (42) formed on the substrate (66) and including a first winding (50) and a second winding (52), each having respective first and second ends, and a reaction circuit component (48) formed on the substrate (66) and electrically coupled to the second winding (52) between the first and second ends thereof. The balun transformer (42) and the reaction circuit component (48) jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component (48) is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.
摘要翻译： 电子组件包括衬底（66），形成在衬底（66）上并包括第一绕组（50）和第二绕组（52）的平衡不平衡变压器（42），每个具有相应的第一和第二端，以及反应 电路部件（48），形成在所述基板（66）上并且在所述第一和第二端之间电连接到所述第二绕组（52）。 平衡 - 不平衡变压器（42）和反应电路部件（48）共同形成具有基频的谐波抑制平衡不平衡变压器，并且调谐反应电路部件（48），使得谐波抑制的平衡不平衡变压器以所选择的谐波谐振 基频
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公开(公告)号：US07608913B2
公开(公告)日：2009-10-27
申请号：US11360285
申请日：2006-02-23
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/823481 , H01L29/0619
摘要： An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.
摘要翻译： 集成电路包括由于在衬底的区域中形成的低掺杂浓度而具有高电阻率的p阱块区域，用于在第一电路块和第二电路块之间提供噪声隔离。 集成电路还包括围绕p阱块区域形成的保护区域，用于在第一电路块和第二电路块之间提供噪声隔离。
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8.发明授权Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate 失效制造半导体部件的方法，其包括将栅电极自对准到场板公开(公告)号：US06939781B2
公开(公告)日：2005-09-06
申请号：US10609106
申请日：2003-06-27
申请人： Randy D. Redd , Paul A. Fisher , Olin L. Hartin , Lawrence S. Klingbeil , Ellen Lan , Hsin-Hua P. Li , Charles E. Weitzel
发明人： Randy D. Redd , Paul A. Fisher , Olin L. Hartin , Lawrence S. Klingbeil , Ellen Lan , Hsin-Hua P. Li , Charles E. Weitzel
IPC分类号： H01L21/338 , H01L29/812 , H01L21/76
CPC分类号： H01L29/66871 , H01L29/402 , H01L29/42316 , H01L29/812
摘要： In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (420) above the semiconductor substrate, a gate electrode (1120) above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate (210) above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer (310) above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer (910) between the gate electrode and the field plate and not located above the gate electrode or the field plate.
摘要翻译： 在本发明的一个实施例中，半导体部件包括半导体衬底（110），半导体衬底上方的第一介电层（120），半导体上方的第一欧姆接触区（410）和第二欧姆接触区（420） 衬底，半导体衬底之上和第一欧姆接触区域和第二欧姆接触区域之间的栅极电极（1120），在第一介电层上方以及栅电极和第二欧姆接触区域之间的场板（210）， 位于场板上方的第二电介质层（310），第一电介质层，第一欧姆接触区域和第二欧姆接触区域，以及栅电极和场板之间的第三介电层（910） 栅电极或场板。
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公开(公告)号：US09048110B2
公开(公告)日：2015-06-02
申请号：US13802006
申请日：2013-03-13
IPC分类号： H01L29/00 , H01L23/552 , H01L29/06 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/8234
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/823481 , H01L29/0619
摘要： An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
摘要翻译： 集成电路包括在衬底的区域中形成的低掺杂浓度的p阱块区域，用于在第一电路块和第二电路块之间提供噪声隔离。 集成电路还包括保护区域和接地的高掺杂区域，用于提供额外的噪声隔离。
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公开(公告)号：US20100026411A1
公开(公告)日：2010-02-04
申请号：US12183755
申请日：2008-07-31
申请人： LIANJUN LIU , Jonathan K. Abrokwah , Olin L. Hartin , Qiang Li
发明人： LIANJUN LIU , Jonathan K. Abrokwah , Olin L. Hartin , Qiang Li
IPC分类号： H03H7/42
CPC分类号： H03H7/42 , H01F19/08 , H01F2017/0046 , H03H7/1758 , H03H7/1766 , H03H7/1775
摘要： A balanced-unbalanced (balun) signal transformer includes an unbalanced port, a balanced port coupled to the unbalanced port, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to the first terminal, a first inductor coupled to ground and the first capacitor, a second capacitor coupled to the second terminal, and a second inductor coupled to ground and the second capacitor. The transformer may also include a third capacitor coupled to a terminal of the unbalanced port; and a third inductor coupled to the third capacitor and the third terminal.
摘要翻译： 平衡不平衡（balun）信号变压器包括不平衡端口，耦合到不平衡端口的平衡端口，平衡端口包括第一端子和第二端子，耦合到第一端子的第一电容器，耦合到地的第一电感器 并且第一电容器，耦合到第二端子的第二电容器和耦合到地的第二电感器和第二电容器。 变压器还可以包括耦合到不平衡端口的端子的第三电容器; 以及耦合到所述第三电容器和所述第三端子的第三电感器。
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